Suresh Vignesh, Kusuma Damar Yoga, Lee Pooi See, Yap Fung Ling, Srinivasan M P, Krishnamoorthy Sivashankar
Department of Chemical and Biomolecular Engineering, National University of Singapore , Blk E5, 4 Engineering Drive 4, Singapore 117576.
ACS Appl Mater Interfaces. 2015 Jan 14;7(1):279-86. doi: 10.1021/am506174s. Epub 2015 Jan 5.
Flash memory devices with high-performance levels exhibiting high charge storage capacity, good charge retention, and high write/erase speeds with lower operating voltages are widely in demand. In this direction, we demonstrate hierarchical self-assembly of gold nanoparticles based on block copolymer templates as a promising route to engineer nanoparticle assemblies with high nanoparticle densities for application in nanocrystal flash memories. The hierarchical self-assembly process allows systematic multiplication of nanoparticle densities with minimal increase in footprint, thereby increasing the charge storage density without an increase in operating voltage. The protocol involves creation of a parent template composed of gold nanoclusters that guides the self-assembly of diblock copolymer reverse micelles which in turn directs electrostatic assembly of gold nanoparticles resulting in a three-level hierarchical system. Capacitance-voltage (C-V) measurements of the hierarchical nanopatterns with a metal-insulator-semiconductor capacitor configuration reveal promising enhancement in memory window as compared to nonhierarchical nanoparticle controls. Capacitance-time (C-t) measurements show that over half the stored charges were retained when extrapolated to 10 years. The fabrication route can be readily extended to programmed density multiplication of features made of other potential charge storage materials such as platinum, palladium, or hybrid metal/metal oxides for next generation, solution-processable flash memory devices.
具有高性能水平的闪存设备,展现出高电荷存储容量、良好的电荷保持能力以及在较低工作电压下的高写入/擦除速度,因而需求量很大。在这一方向上,我们展示了基于嵌段共聚物模板的金纳米颗粒分层自组装,这是一种很有前景的途径,可用于设计具有高纳米颗粒密度的纳米颗粒组件,以应用于纳米晶体闪存。分层自组装过程允许在占地面积增加最小的情况下系统地增加纳米颗粒密度,从而在不增加工作电压的情况下提高电荷存储密度。该方案包括创建由金纳米团簇组成的母模板,该模板引导双嵌段共聚物反胶束的自组装,而双嵌段共聚物反胶束又指导金纳米颗粒的静电组装,从而形成一个三级分层系统。采用金属-绝缘体-半导体电容器配置对分层纳米图案进行的电容-电压(C-V)测量表明,与非分层纳米颗粒对照相比,记忆窗口有了显著增强。电容-时间(C-t)测量表明,外推至10年时,超过一半的存储电荷得以保留。这种制造路线可以很容易地扩展到由其他潜在电荷存储材料(如铂、钯或混合金属/金属氧化物)制成的特征的编程密度倍增,用于下一代可溶液处理的闪存设备。