A 0.83- μW QRS detection processor using quadratic spline wavelet transform for wireless ECG acquisition in 0.35- μm CMOS.

Healthcare electronics count on the effectiveness of the on-patient signal preprocessing unit to moderate the wireless data transfer for better power efficiency. In order to reduce the system power in long-time ECG acquisition, this work describes an on-patient QRS detection processor for arrhythmia monitoring. It extracts the concerned ECG part, i.e., the RR-interval between the QRS complex for evaluating the heart rate variability. The processor is structured by a scale-3 quadratic spline wavelet transform followed by a maxima modulus recognition stage. The former is implemented via a symmetric FIR filter, whereas the latter includes a number of feature extraction steps: zero-crossing detection, peak (zero-derivative) detection, threshold adjustment and two finite state machines for executing the decision rules. Fabricated in 0.35-μm CMOS the 300-Hz processor draws only 0.83 μW, which is favorably comparable with the prior arts. In the system tests, the input data is placed via an on-chip 10-bit SAR analog-to-digital converter, while the output data is emitted via an off-the-shelf wireless transmitter (TI CC2500) that is configurable by the processor for different data transmission modes: 1) QRS detection result, 2) raw ECG data or 3) both. Validated with all recordings from the MIT-BIH arrhythmia database, 99.31% sensitivity and 99.70% predictivity are achieved. Mode 1 with solely the result of QRS detection exhibits 6× reduction of system power over modes 2 and 3.