Lee Kwan-Hee, Lee Sang-Jin, Kim Seok-Man, Cho Kyoungrok
College of Electrical and Computer Engineering, Chungbuk National University, Cheongju, Chungbuk, South Korea.
J Nanosci Nanotechnol. 2013 May;13(5):3265-9. doi: 10.1166/jnn.2013.7260.
A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors.
蔡少棠在1971年提出的忆阻器有可能极大地影响电子电路的设计方式。它是一种双端器件，其电阻状态基于在其两端施加电压所导致的电荷流动历史，因此可以被视为可重构电阻器的一种特殊情况。使用忆阻器交叉阵列等密集且规则结构的纳米级器件，对于片上系统（SoC）实现而言是一种很有前景的新架构，这不仅体现在该技术所能提供的集成密度上，还体现在性能的提升和功耗的降低上。忆阻器能够在交叉阵列电路配置中在高电阻状态和低电阻状态之间切换。交叉阵列由垂直导电纳米线阵列与水平导电线路的第二个阵列交叉形成。通过适当的处理技术在阵列中两条线的交叉点处实现忆阻器，使得垂直阵列中的任何特定导线可以通过将特定交叉点的电阻切换到低状态而连接到水平阵列中的一条导线，同时其他交叉点保持在高电阻状态。然而，这种方法带来了许多挑战。电压增益的缺乏阻止了逻辑的级联，并且电压电平的下降影响了操作的稳健性。此外，当两个或更多交叉点通过开关忆阻器连接时，交叉阵列会引入潜行电流路径。在本文中，我们提出了基于忆阻器的可编程逻辑阵列（PLA）架构，并开发了一个分析模型来分析忆阻网络上的逻辑电平。所提出的PLA架构最多有12个输入，并且对于忆阻器的R（off）/R（on）比率在55到160范围内的更多输入变量可以进行级联。
