Department of EE, Chungbuk National University, 1 Chungdae-ro Seowon-gu, Cheongju, 28644, S. Korea.
School of EE, University of Western Australia, 35 Stirling Hwy, Crawley WA, 6009, Australia.
J Nanosci Nanotechnol. 2019 Mar 1;19(3):1295-1300. doi: 10.1166/jnn.2019.16239.
The memristor, as theorized by Chua in 1971 (L. Chua, 18, 507 (1971)), is a two-terminal device whose resistance state is based on the history of charge flow brought about as a result of the voltage applied across its terminals. High-density regular fabrics for nanoscale memristors, such as crossbar arrays, are emerging architectures for system-on-chip (SoC) implementation, which provide both simplified structure and improved performance (W. H. Yu, et al., 20, 1012 (2012)). The advantage of using memristors as the switching devices within crossbar arrays is their nanoscale switching capability, which specifically changes their resistance state between high and low. In this paper, we propose a new nano-programmable logic array (PLA) device in the form of an on anti-facing double-layer memristor array. The PLA is composed of an AND plane and an OR plane merged onto the same layer. The AND and OR planes are stacked vertically such that each layer forms a crossbar architecture; thus, a cross section reveals two anti-facing memristors with 5 layers: the bottom metal layer, a memristive layer, the intermediate metal layer, an anti-facing memristive layer, and the top metal layer. The intermediate metal layer provides its output at the AND plane which is the input of the OR plane, and as such, the input and output nodes of the two logic functions are shared. Thus, the proposed architecture reduces the propagation delay of the AND plane by 70% by sharing the OR plane input wires. Additionally, the anti-facing architecture makes it easy to determine appropriate values for the pull-up and pull-down registers of the PLA.
忆阻器，由蔡少棠于 1971 年提出理论（L. Chua, 18, 507 (1971)），是一种具有两个终端的器件，其电阻状态基于在其两端施加电压所产生的电荷流动历史。用于纳米级忆阻器的高密度规则结构，如交叉阵列，是面向片上系统 (SoC) 实现的新兴架构，它们提供了简化的结构和改进的性能（W. H. Yu 等人，20, 1012 (2012)）。在交叉阵列中使用忆阻器作为开关器件的优势在于其纳米级开关能力，这特别可以在高低之间改变其电阻状态。在本文中，我们提出了一种新的纳米可编程逻辑阵列 (PLA) 器件，其形式为反面对双层忆阻器阵列。PLA 由与平面和或平面合并到同一层组成。与平面和或平面垂直堆叠，使得每层形成交叉架构；因此，横截面显示出两个反面对的具有 5 层的忆阻器：底层金属层、忆阻层、中间金属层、反面对的忆阻层和顶层金属层。中间金属层在与平面提供输出，这是或平面的输入，因此，两个逻辑函数的输入和输出节点共享。因此，通过共享或平面输入线，所提出的架构将与平面的传播延迟减少了 70%。此外，反面对的架构使得确定 PLA 的上拉和下拉寄存器的适当值变得容易。
