Low-temperature plasma etching of high aspect-ratio densely packed 15 to sub-10 nm silicon features derived from PS-PDMS block copolymer patterns.

The combination of block copolymer (BCP) lithography and plasma etching offers a gateway to densely packed sub-10 nm features for advanced nanotechnology. Despite the advances in BCP lithography, plasma pattern transfer remains a major challenge. We use controlled and low substrate temperatures during plasma etching of a chromium hard mask and then the underlying substrate as a route to high aspect ratio sub-10 nm silicon features derived from BCP lithography. Siloxane masks were fabricated using poly(styrene-b-siloxane) (PS-PDMS) BCP to create either line-type masks or, with the addition of low molecular weight PS-OH homopolymer, dot-type masks. Temperature control was essential for preventing mask migration and controlling the etched feature's shape. Vertical silicon wire features (15 nm with feature-to-feature spacing of 26 nm) were etched with aspect ratios up to 17 : 1; higher aspect ratios were limited by the collapse of nanoscale silicon structures. Sub-10 nm fin structures were etched with aspect ratios greater than 10 : 1. Transmission electron microscopy images of the wires reveal a crystalline silicon core with an amorphous surface layer, just slightly thicker than a native oxide.