Puhan Janez, Raič Dušan, Tuma Tadej, Bűrmen Árpád
Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.
ScientificWorldJournal. 2014;2014:349131. doi: 10.1155/2014/349131. Epub 2014 Nov 26.
A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.
为了在需要慢速操作的情况下增加延迟并降低功耗开销，提出了一种具有两个输入和两个输出的改进型静态互补金属氧化物半导体（CMOS）反相器，以减少短路电流。该电路基于与PMOS和NMOS开关晶体管串联连接的双向延迟元件。它提供了动态响应方面的差异，从而降低了下一级的直接路径电流。开关晶体管不会同时导通。给出了各种延迟元件实现方式的特性，并通过电路仿真进行了验证。采用全局优化程序来获得最节能的晶体管尺寸。将改进后的CMOS反相器链的性能与各种延迟情况下的标准实现方式进行了比较。每个延迟的能量（电荷）最多可降低40%。通过实现一个低功耗延迟线和一个前沿检测单元，展示了所提出的延迟元件的应用。
