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亚10纳米聚三甲基硅烷-b-聚甲基辛基硅氧烷的双图案侧壁定向自组装及图案转移

Double-Patterned Sidewall Directed Self-Assembly and Pattern Transfer of Sub-10 nm PTMSS-b-PMOST.

作者信息

Cushen Julia, Wan Lei, Blachut Gregory, Maher Michael J, Albrecht Thomas R, Ellison Christopher J, Willson C Grant, Ruiz Ricardo

机构信息

†HGST, a Western Digital Company, 3403 Yerba Buena Rd., San Jose, California 95135, United States.

‡The University of Texas at Austin, McKetta Department of Chemical Engineering, 200 E Dean Keeton St. Stop C0400, Austin, Texas 78712, United States.

出版信息

ACS Appl Mater Interfaces. 2015 Jun 24;7(24):13476-83. doi: 10.1021/acsami.5b02481. Epub 2015 Jun 10.

Abstract

The directed self-assembly (DSA) of two sub-20 nm pitch silicon-containing block copolymers (BCPs) was accomplished using a double-patterned sidewall scheme in which each lithographic prepatterned feature produced two regions for pattern registration. In doing so, the critical dimension of the lithographic prepatterns was relaxed by a factor of 2 compared to previously reported schemes for DSA. The key to enabling the double-patterned sidewall scheme is the exploitation of the oxidized sidewalls of cross-linked polystyrene formed during the pattern transfer of the resist via reactive ion etching. This results in shallow trenches with two guiding interfaces per prepatterned feature. Electron loss spectroscopy was used to study and confirm the guiding mechanism of the double-patterned sidewalls, and pattern transfer of the BCPs into a silicon substrate was achieved using reactive ion etching. The line edge roughness, width roughness, and placement error are near the target required for bit-patterned media applications, and the technique is also compatible with the needs of the semiconductor industry for high-volume manufacturing.

摘要

通过双图案侧壁方案实现了两种亚20纳米间距含硅嵌段共聚物(BCP)的定向自组装(DSA),其中每个光刻预图案化特征产生两个用于图案对准的区域。这样做时,与先前报道的DSA方案相比,光刻预图案的关键尺寸放宽了2倍。实现双图案侧壁方案的关键在于利用在抗蚀剂通过反应离子蚀刻进行图案转移期间形成的交联聚苯乙烯的氧化侧壁。这导致每个预图案化特征具有两个引导界面的浅沟槽。使用电子能量损失谱来研究和确认双图案侧壁的引导机制,并通过反应离子蚀刻将BCP图案转移到硅衬底中。线边缘粗糙度、宽度粗糙度和位置误差接近位图案介质应用所需的目标,并且该技术也符合半导体行业大规模制造的需求。

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