Jain Sanjeev Kumar, Bhaumik Basabi
Annu Int Conf IEEE Eng Med Biol Soc. 2015 Aug;2015:857-60. doi: 10.1109/EMBC.2015.7318497.
This paper presents an ultra low power ASIC design based on a new cardiovascular disease diagnostic algorithm. This new algorithm based on forward search is designed for real time ECG signal processing. The algorithm is evaluated for Physionet PTB database from the point of view of cardiovascular disease diagnosis. The failed detection rate of QRS complex peak detection of our algorithm ranges from 0.07% to 0.26% for multi lead ECG signal. The ASIC is designed using 130-nm CMOS low leakage process technology. The area of ASIC is 1.21 mm(2). This ASIC consumes only 96 nW at an operating frequency of 1 kHz with a supply voltage of 0.9 V. Due to ultra low power consumption, our proposed ASIC design is most suitable for energy efficient wearable ECG monitoring devices.
本文介绍了一种基于新型心血管疾病诊断算法的超低功耗专用集成电路（ASIC）设计。这种基于前向搜索的新算法专为实时心电图（ECG）信号处理而设计。从心血管疾病诊断的角度对该算法在Physionet PTB数据库上进行了评估。对于多导联ECG信号，我们算法的QRS复合波峰值检测失败率在0.07%至0.26%之间。该ASIC采用130纳米CMOS低泄漏工艺技术设计。ASIC的面积为1.21平方毫米。该ASIC在工作频率为1千赫兹、电源电压为0.9伏时仅消耗96纳瓦功率。由于超低功耗，我们提出的ASIC设计最适合用于节能型可穿戴ECG监测设备。
