Effect of carrier tunneling on the structure of Si nanowires fabricated by metal assisted etching.

The metal assisted etching mechanism for Si nanowire fabrication, triggered by doping type and level and coupled with choice of metal catalyst, is still very poorly understood. We explain the different etching rates and porosities of wires we observe based on extensive experimental data, using a new empirical model we have developed. We establish as a key parameter, the tunneling through the space charge region (SCR) which is the result of the reduction of the SCR width by level of the Si wafer doping in the presence of the opposite biases of the p- and n-type wafers. This improved understanding should permit the fabrication of high quality wires with predesigned structural characteristics, which hitherto has not been possible.