The Proposed MACRA/MIPS Threshold for Patient-Facing Encounters: What It Means for Radiologists.

PURPOSE

In implementing the Merit-Based Incentive Payment System (MIPS), CMS will provide special considerations to physicians with infrequent face-to-face patient encounters by reweighting MIPS performance categories to account for the unique circumstances facing these providers. The aim of this study was to determine the impact of varying criteria on the fraction of radiologists who are likely to receive special considerations for performance assessment under MIPS.

METHODS

Data from the 2014 Medicare Physician and Other Supplier file for 28,710 diagnostic radiologists were used to determine the fraction of radiologists meeting various proposed criteria for receiving special considerations. For each definition, the fraction of patient-facing encounters among all billed codes was determined for those radiologists not receiving special considerations.

RESULTS

When using the criterion proposed by CMS that physicians will receive special considerations if billing ≤25 evaluation and management services or surgical codes, 72.0% of diagnostic radiologists would receive special considerations, though such encounters would represent only 2.1% of billed codes among remaining diagnostic radiologists without special considerations. If CMS were to apply an alternative criterion of billing ≤100 evaluation and management codes exclusively, 98.8% of diagnostic radiologists would receive special considerations. At this threshold, patient-facing encounters would represent approximately 10% of billed codes among remaining radiologists without special considerations.

CONCLUSIONS

The current CMS proposed criterion for special considerations would result in a considerable fraction of radiologists being evaluated on the basis of measures that are not reflective of their practice and beyond their direct control. Alternative criteria could help ensure that radiologists are provided a fair opportunity for success in performance review under the MIPS.