Fernández Enric, Calero David, Parés M Eulàlia
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC/CERCA), Parc Mediterrani de la Tecnologia (PMT), Building B4, Av. Carl Friedrich Gauss 7, 08860 Castelldefels, Spain.
Sensors (Basel). 2017 Feb 14;17(2):370. doi: 10.3390/s17020370.
Chip Scale Atomic Clocks (CSAC) are recently-developed electronic instruments that, when used together with a Global Navigation Satellite Systems (GNSS) receiver, help improve the performance of GNSS navigation solutions in certain conditions (i.e., low satellite visibility). Current GNSS receivers include a Temperature Compensated Cristal Oscillator (TCXO) clock characterized by a short-term stability ( = 1 s) of 10 s that leads to an error of 0.3 m in pseudorange measurements. The CSAC can achieve a short-term stability of 2.5 × 10 s, which implies a range error of 0.075 m, making for an 87.5% improvement over TCXO. Replacing the internal TCXO clock of GNSS receivers with a higher frequency stability clock such as a CSAC oscillator improves the navigation solution in terms of low satellite visibility positioning accuracy, solution availability, signal recovery (holdover), multipath and jamming mitigation and spoofing attack detection. However, CSAC suffers from internal systematic instabilities and errors that should be minimized if optimal performance is desired. Hence, for operating CSAC at its best, the deterministic errors from the CSAC need to be properly modelled. Currently, this modelling is done by determining and predicting the clock frequency stability (i.e., clock bias and bias rate) within the positioning estimation process. The research presented in this paper aims to go a step further, analysing the correlation between temperature and clock stability noise and the impact of its proper modelling in the holdover recovery time and in the positioning performance. Moreover, it shows the potential of fine clock coasting modelling. With the proposed model, an improvement in vertical positioning precision of around 50% with only three satellites can be achieved. Moreover, an increase in the navigation solution availability is also observed, a reduction of holdover recovery time from dozens of seconds to only a few can be achieved.
芯片级原子钟（CSAC）是最近开发的电子仪器，与全球导航卫星系统（GNSS）接收器一起使用时，有助于在某些条件下（即卫星可见度低）提高GNSS导航解决方案的性能。当前的GNSS接收器包括一个温度补偿晶体振荡器（TCXO）时钟，其短期稳定性（=1秒）为10^-6，这会导致伪距测量中出现0.3米的误差。CSAC可以实现2.5×10^-8的短期稳定性，这意味着距离误差为0.075米，比TCXO提高了87.5%。用更高频率稳定性的时钟（如CSAC振荡器）取代GNSS接收器的内部TCXO时钟，可在低卫星可见度定位精度、解决方案可用性、信号恢复（保持）、多径和干扰缓解以及欺骗攻击检测方面改善导航解决方案。然而，CSAC存在内部系统不稳定性和误差，如果需要最佳性能，应将其降至最低。因此，为了使CSAC发挥最佳性能，需要对CSAC的确定性误差进行适当建模。目前，这种建模是通过在定位估计过程中确定和预测时钟频率稳定性（即时钟偏差和偏差率）来完成的。本文提出的研究旨在更进一步，分析温度与时钟稳定性噪声之间的相关性及其在保持恢复时间和定位性能方面的适当建模的影响。此外，它还展示了精细时钟滑行建模的潜力。使用所提出的模型，仅使用三颗卫星就能实现垂直定位精度提高约50%。此外，还观察到导航解决方案可用性的提高，保持恢复时间从几十秒减少到只有几秒。
