基于双栅隧穿晶体管的无电容动态随机存取存储器的间隔工程优化

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor.

作者信息

Li Wei, Liu Hongxia, Wang Shulong, Chen Shupeng, Wang Qianqiong

机构信息

Key Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University, Xi'an, 710071, China.

出版信息

Nanoscale Res Lett. 2018 Mar 5;13(1):73. doi: 10.1186/s11671-018-2483-8.

DOI:10.1186/s11671-018-2483-8

PMID:29508093

原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC5838025/

Abstract

The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (10) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

摘要

基于双栅隧穿场效应晶体管（DGTFET）的动态随机存取存储器（DRAM）具有无电容器结构和高数据保持时间的优点。本文利用Silvaco-Atlas工具系统地研究了DGTFET DRAM的间隔层工程优化，以进一步提高其性能，包括降低读“0”电流和延长数据保持时间。仿真结果表明，源极和漏极侧的间隔层应分别采用低介电常数和高介电常数电介质，这可以增强读“1”电流并降低读“0”电流。应用这种优化的间隔层工程，DGTFET DRAM获得了最佳性能——极低的读“0”电流（10 A/μm）和长数据保持时间（10 s），这降低了其静态功耗和动态刷新速率。而且低读“0”电流还提高了其读“1”与读“0”的电流比（10）。此外，关于可扩展性的分析揭示了其固有缺点，这为DGTFET DRAM提供了进一步的研究方向。