Akgul Mehmet, Ozgurluk Alper, Nguyen Clark T-C
IEEE Trans Ultrason Ferroelectr Freq Control. 2019 Jan;66(1):218-235. doi: 10.1109/TUFFC.2018.2883296. Epub 2018 Nov 26.
This Part II of a two-paper sequence presents fabrication and measurement results for a micromechanical disk-based RF channel-select filter designed using the theory and procedure of Part I. Successful demonstration of an actual filter required several practical additions to an ideal design, including the introduction of a 39-nm-gap capacitive transducer, voltage-controlled frequency tuning electrodes, and a stress relieving coupled array design, all of which combine to enable a 0.1% bandwidth 223.4-MHz channel-select filter with only 2.7 dB of in-band insertion loss and 50-dB rejection of out-of-band interferers. This amount of rejection is more than 23 dB better than a previous capacitive-gap transduced filter design that did not benefit from sub-50-nm gaps. It also comes in tandem with a 20-dB shape factor of 2.7 realized by a hierarchical mechanical circuit design utilizing 206 micromechanical circuit elements, all contained in an area footprint of only [Formula: see text]. The key to such low insertion loss for this tiny percent bandwidth is Q 's >8800 supplied by polysilicon disk resonators employing for the first time capacitive transducer gaps small enough to generate coupling strengths of C/C ∼ 0.1 %, which is a 6.1× improvement over previous efforts. The filter structure utilizes electrical tuning to correct frequency mismatches due to process variations, where a dc tuning voltage of 12.1 V improves the filter insertion loss by 1.8 dB and yields the desired equiripple passband shape. Measured filter performance, both in- and out-of-channel, compares well with predictions of an electrical equivalent circuit that captures not only the ideal filter response, but also parasitic nonidealities that distort somewhat the filter response.
本两篇论文系列的第二部分展示了基于微机械盘的射频通道选择滤波器的制造和测量结果,该滤波器是使用第一部分的理论和程序设计的。要成功演示一个实际的滤波器,需要在理想设计上进行一些实际的改进,包括引入39纳米间隙的电容式换能器、压控频率调谐电极和应力消除耦合阵列设计,所有这些结合起来可实现带宽为0.1%、中心频率为223.4兆赫兹的通道选择滤波器,其带内插入损耗仅为2.7分贝,对带外干扰的抑制比为50分贝。这种抑制比优于之前未受益于亚50纳米间隙的电容式间隙换能器滤波器设计超过23分贝。它还与通过利用206个微机械电路元件的分层机械电路设计实现的2.7的20分贝形状因数相伴,所有这些元件都包含在仅[公式:见正文]的面积范围内。对于如此小百分比带宽实现低插入损耗的关键在于,首次采用电容式换能器间隙足够小以产生C/C ∼ 0.1%耦合强度的多晶硅盘谐振器提供的Q值>8800,这比之前的努力提高了6.1倍。滤波器结构利用电调谐来校正由于工艺变化引起的频率失配,其中12.1伏的直流调谐电压可将滤波器插入损耗提高1.8分贝,并产生所需的等波纹通带形状。测量得到的滤波器在通道内和通道外的性能与电等效电路的预测结果比较吻合,该等效电路不仅捕捉了理想滤波器响应,还考虑了会使滤波器响应略有失真的寄生非理想因素。