Electrical Engineering and Computer Sciences , University of California, Berkeley , Berkeley , California 94720 , United States.
Materials Sciences Division , Lawrence Berkeley National Laboratory , Berkeley , California 94720 , United States.
Nano Lett. 2019 Oct 9;19(10):7130-7137. doi: 10.1021/acs.nanolett.9b02660. Epub 2019 Sep 23.
As the physical dimensions of a transistor gate continue to shrink to a few atoms, performance can be increasingly determined by the limited electronic density of states (DOS) in the gate and the gate quantum capacitance (). We demonstrate the impact of gate and the dimensionality of the gate electrode on the performance of nanoscale transistors through analytical electrostatics modeling. For low-dimensional gates, the gate charge can limit the channel charge, and the transfer characteristics of the device become dependent on the gate DOS. We experimentally observe for the first time, room-temperature gate quantization features in the transfer characteristics of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) channel transistors; features which can be attributed to the Van Hove singularities in the one-dimensional DOS of the CNT gate. In addition to being an important aspect of future transistor design, potential applications of this phenomenon include multilevel transistors with suitable transfer characteristics obtained via engineered gate DOS.
随着晶体管栅极的物理尺寸持续缩小到几个原子，性能越来越取决于栅极中的有限电子态密度 (DOS) 和栅极量子电容 (). 通过分析静电建模，我们展示了栅极和栅极电极的维度对纳米尺度晶体管性能的影响。对于低维栅极，栅极电荷会限制沟道电荷，并且器件的转移特性取决于栅极 DOS。我们首次实验观察到，在单壁碳纳米管 (CNT)-栅极超浅硅绝缘体 (SOI) 通道晶体管的转移特性中存在室温栅极量子化特征；这些特征可归因于 CNT 栅极的一维 DOS 中的范霍夫奇点。除了是未来晶体管设计的一个重要方面外，这种现象的潜在应用包括通过工程化栅极 DOS 获得合适转移特性的多级晶体管。
