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使用并联电阻-电感-电容 (RLC) 电路提高神经活动的电阻抗断层成像中的信号幅度。

Increasing signal amplitude in electrical impedance tomography of neural activity using a parallel resistor inductor capacitor (RLC) circuit.

机构信息

The Department of Mechanical Engineering, The University of Auckland, Auckland, New Zealand. Dodd Walls Centre for Photonic and Quantum Technologies, Dunedin, New Zealand.

出版信息

J Neural Eng. 2019 Nov 11;16(6):066041. doi: 10.1088/1741-2552/ab462b.

Abstract

OBJECTIVE

To increase the impedance signal amplitude produced during neural activity using a novel approach of implementing a parallel resistor inductor capacitor (RLC) circuit across the current source used in electrical impedance tomography (EIT) of peripheral nerve.

APPROACH

The frequency response of the impedance signal was characterized in the range 4-18 kHz, then a frequency range with significant capacitive charge transfer was selected for experiment with the RLC circuit. Design of the RLC circuit was aided by in vitro impedance measurements on nerve and nerve cuff in the range 5 Hz to 50 kHz.

MAIN RESULTS

The frequency response of the impedance signal across 4-18 kHz showed maximum amplitude at 6-8 kHz, and steady decline in amplitude between 8 and 18 kHz with  -6 dB reduction at 14 kHz. The frequency range 17  ±  1 kHz was selected for the RLC experiment. The RLC experiment was performed on four subjects using an RLC circuit designed to produce a resonant frequency of 17 kHz with a bandwidth of 3.6 kHz, and containing a 22 mH inductive element and a 3.45 nF capacitive element with  +0.8/-  3.45 nF manual tuning range. With the RLC circuit connected, relative increases in the impedance signal (±3σ noise) of 44% (±15%), 33% (±30%), 37% (±8.6%), and 16% (±19%) were produced.

SIGNIFICANCE

The increase in impedance signal amplitude at high frequencies, generated by the novel implementation of a parallel RLC circuit across the drive current, improves spatial resolution by increasing the number of parallel drive currents which can be implemented in a frequency division multiplexed (FDM) EIT system, and aids the long term goal of a real-time FDM EIT system by reducing the need for ensemble averaging.

摘要

目的

通过在用于周围神经电阻抗断层成像(EIT)的电流源上实现并联电阻-电感-电容(RLC)电路,提高神经活动过程中产生的阻抗信号幅度。

方法

在 4-18 kHz 的范围内对阻抗信号的频率响应进行了特征描述,然后选择具有显著电容电荷转移的频率范围进行 RLC 电路实验。在 5 Hz 至 50 kHz 的范围内对神经和神经袖套进行体外阻抗测量,以辅助 RLC 电路的设计。

主要结果

在 4-18 kHz 范围内,阻抗信号的频率响应在 6-8 kHz 处达到最大幅度,在 8-18 kHz 之间幅度稳定下降,在 14 kHz 处减少 6 dB。选择 17 ± 1 kHz 的频率范围进行 RLC 实验。在四个对象上进行了 RLC 实验,使用设计产生 17 kHz 谐振频率和 3.6 kHz 带宽的 RLC 电路,其中包含 22 mH 电感元件和 3.45 nF 电容元件,具有 +0.8/-3.45 nF 的手动调谐范围。连接 RLC 电路后,阻抗信号(±3σ 噪声)相对增加了 44%(±15%)、33%(±30%)、37%(±8.6%)和 16%(±19%)。

意义

通过在驱动电流上实现并联 RLC 电路的新方法,在高频产生的阻抗信号幅度增加,通过增加可在频分复用(FDM)EIT 系统中实现的并行驱动电流的数量,提高了空间分辨率,并通过减少对集合平均的需求,有助于实时 FDM EIT 系统的长期目标。

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