State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, PR China.
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, PR China.
J Colloid Interface Sci. 2020 Feb 15;560:769-776. doi: 10.1016/j.jcis.2019.10.041. Epub 2019 Nov 7.
Metal oxide/semiconductor heterostructures exhibit great potential for high-performance electronic device applications, but the interfacial defects resulting from lattice mismatch pose significant challenges to improving the performance of these devices. In this study, we reported a construction of a single crystal TiO/GaAs heterostructure with minimum lattice mismatch between titanium sub-oxides and GaAs substrate. Low lattice mismatch values of 0.3% or 0.6% can be achieved along different orientations. Further experimental analyses demonstrate that high crystalline TiO (0 1 0) film can be grown layer by layer on GaAs (0 0 1) substrate with highly compatible interface. The defect-free interface significantly suppresses the diffusion of As and Ga ions, which impedes the formation of arsenic oxide and gallium oxide at the interface. Due to the high-quality TiO layer, the integrated BaTiO(250 nm)/SrTiO/TiO(5 nm)/GaAs heterostructure exhibits an enhanced hysteresis loop with a remnant polarization of 9.85 µC/cm at 600 kV/cm and a small leakage current density of 1 × 10 A/cm at -500 kV/cm. The considerable advantage of this TiO/GaAs heterostructure provides an example of integrating other functional oxides for GaAs with suppressed ion diffusion. It also provides a platform for fabricating different electronic devices with higher reliability and performance.
金属氧化物/半导体异质结构在高性能电子器件应用方面具有巨大的潜力，但晶格失配导致的界面缺陷对提高这些器件的性能构成了重大挑战。在本研究中，我们报告了一种具有最小钛亚氧化物与 GaAs 衬底晶格失配的单晶 TiO/GaAs 异质结构的构建。沿着不同的取向可以实现低至 0.3%或 0.6%的晶格失配值。进一步的实验分析表明，高结晶性的 TiO(010)薄膜可以在 GaAs(001)衬底上逐层生长，具有高度兼容的界面。无缺陷的界面显著抑制了 As 和 Ga 离子的扩散，阻碍了界面处砷氧化物和氧化镓的形成。由于高质量的 TiO 层，集成的 BaTiO(250nm)/SrTiO/TiO(5nm)/GaAs 异质结构在 600kV/cm 时表现出增强的滞后回线，剩余极化率为 9.85µC/cm，在-500kV/cm 时漏电流密度为 1×10A/cm。这种 TiO/GaAs 异质结构的巨大优势为抑制离子扩散的 GaAs 集成其他功能氧化物提供了一个范例。它还为制造具有更高可靠性和性能的不同电子器件提供了一个平台。
