Department Electrical and Information Technologies Engineering (DIETI), University of Naples Federico II, via Claudio 21, 80125 Naples, Italy.
Sensors (Basel). 2020 Mar 14;20(6):1619. doi: 10.3390/s20061619.
Fine resolution selection of the sample rate is not available in digital storage oscilloscopes (DSOs), so the user has to rely on offline processing to cope with such need. The paper first discusses digital signal processing based methods that allow changing the sampling rate by means of digital resampling approaches. Then, it proposes a digital circuit that, if included in the acquisition channel of a digital storage oscilloscope, between the internal analog-to-digital converter (ADC) and the acquisition memory, allows the user to select any sampling rate lower than the maximum one with fine resolution. The circuit relies both on the use of a short digital filter with dynamically generated coefficients and on a suitable memory management strategy. The output samples produced by the digital circuit are characterized by a sampling rate that can be incoherent with the clock frequency regulating the memory access. Both a field programmable gate array (FPGA) implementation and an application specific integrated circuit (ASIC) design of the proposed circuit are evaluated.
数字存储示波器（DSO）无法进行精细的采样率分辨率选择，因此用户必须依靠离线处理来满足这种需求。本文首先讨论了基于数字信号处理的方法，这些方法允许通过数字重采样方法来改变采样率。然后，本文提出了一种数字电路，如果将其包含在数字存储示波器的采集通道中，位于内部模数转换器（ADC）和采集存储器之间，则允许用户以精细分辨率选择低于最大采样率的任何采样率。该电路既依赖于使用具有动态生成系数的短数字滤波器，也依赖于适当的存储管理策略。数字电路生成的输出样本的采样率可以与调节存储访问的时钟频率不同步。本文评估了该电路的现场可编程门阵列（FPGA）实现和专用集成电路（ASIC）设计。
