Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China.
University of Chinese Academy of Sciences, Beijing 100049, China.
Sensors (Basel). 2022 Aug 5;22(15):5852. doi: 10.3390/s22155852.
A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input-driven by the analog input and by the reference slope generated by an FPGA output buffer-is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between -0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from -0.72 to 0.78 LSB.
本文提出了一种斜坡模数转换器 (ADC)，可完全在数字现场可编程门阵列 (FPGA) 上实现，无需任何外部有源或无源元件。幅度信息由 FPGA 输出缓冲器生成的参考斜率和模拟输入驱动的标准 LVDS 差分输入的转换时间编码，并由 FPGA 时间数字转换器检索。与 ADC 一起，开发了一种新的在线校准算法，以减轻其性能对工艺、电压和温度变化的影响。对 ADC 原型的测量结果显示，模拟输入范围为 0.3 V 至 1.5 V，最低有效位 (LSB) 为 2.6 mV，有效位数 (ENOB) 在 600 MS/s 时为 7.4 位。差分非线性 (DNL) 在-0.78 至 0.70 LSB 之间，积分非线性 (INL) 在-0.72 至 0.78 LSB 之间。
