Unaffiliated, Nur-Sultan, Kazakhstan.
Analogue Circuits and Image Sensors, Siegen University, Siegen, 57080, Germany.
Sci Rep. 2020 Apr 3;10(1):5838. doi: 10.1038/s41598-020-62676-7.
Generative Adversarial Network (GAN) requires extensive computing resources making its implementation in edge devices with conventional microprocessor hardware a slow and difficult, if not impossible task. In this paper, we propose to accelerate these intensive neural computations using memristive neural networks in analog domain. The implementation of Analog Memristive Deep Convolutional GAN (AM-DCGAN) using Generator as deconvolutional and Discriminator as convolutional memristive neural network is presented. The system is simulated at circuit level with 1.7 million memristor devices taking into account memristor non-idealities, device and circuit parameters. The design is modular with crossbar arrays having a minimum average power consumption per neural computation of 47nW. The design exclusively uses the principles of neural network dropouts resulting in regularization and lowering the power consumption. The SPICE level simulation of GAN is performed with 0.18 μm CMOS technology and WO memristive devices with R = 40 kΩ and R = 250 kΩ, threshold voltage 0.8 V and write voltage at 1.0 V.
生成对抗网络 (GAN) 需要大量的计算资源，因此在传统微处理器硬件的边缘设备中实现它是一项缓慢而困难的任务，如果不是不可能的话。在本文中，我们提出使用模拟域中的忆阻器神经网络来加速这些密集的神经计算。提出了使用生成器作为解卷积网络和鉴别器作为卷积忆阻器神经网络的模拟忆阻深度卷积 GAN (AM-DCGAN) 的实现。该系统在电路级进行模拟，使用 170 万个忆阻器器件，考虑到忆阻器的非理想性、器件和电路参数。该设计是模块化的，具有交叉阵列，每个神经计算的平均功率消耗最小为 47nW。该设计完全使用神经网络随机失活的原理，从而实现正则化和降低功耗。使用 0.18μm CMOS 技术和 R = 40kΩ 和 R = 250kΩ、阈值电压 0.8V 和写入电压 1.0V 的 WO 忆阻器器件在 SPICE 级对 GAN 进行了仿真。
