Nadweh Safwan, Khaddam Ola, Hayek Ghassan, Atieh Bassan, Haes Alhelou Hassan
Electrical Power Engineering, Tishreen University, Lattakia, Syria.
Mechatronics Engineering, Manara University, Lattakia, Syria.
Heliyon. 2020 Aug 16;6(8):e04739. doi: 10.1016/j.heliyon.2020.e04739. eCollection 2020 Aug.
This research introduces a filtering circuit design integrated with the DC-link of a medium power variable speed drive (VSD) system. The designed filtering circuit employs modern power electronic circuits to improve time response characteristics in both grid and dc-link sides. Depending on the widely used multi-level converters, a conventional three-level H-bridge four-quadrant chopper scheme was developed into a cascade five-level H-bridge four-quadrant chopper scheme. The time response of the proposed system was performed with both choppers, and results showed that voltage drop on cascade chopper transistors was reduced to half in comparison with voltage drop on conventional four-quadrant chopper transistors. Moreover, the sharp fluctuations in system's waves were mitigated; consequently, time response characteristics in both steady and transient states were remarkably improved. The total harmonic distortion factor THD% of the input current and voltage was reduced to 26.2% and 2.43% respectively and the ripple factor RF for DC-link current was reduced to 0.196.
本研究介绍了一种与中功率变速驱动（VSD）系统的直流母线集成的滤波电路设计。所设计的滤波电路采用现代电力电子电路来改善电网侧和直流母线侧的时间响应特性。基于广泛使用的多电平变换器，将传统的三电平H桥四象限斩波器方案发展为级联五电平H桥四象限斩波器方案。对所提出系统的两种斩波器进行了时间响应测试，结果表明，与传统四象限斩波器晶体管上的电压降相比，级联斩波器晶体管上的电压降降低到了一半。此外，系统波形中的急剧波动得到了缓解；因此，稳态和瞬态下的时间响应特性都得到了显著改善。输入电流和电压的总谐波失真因数THD%分别降低到了26.2%和2.43%，直流母线电流的纹波因数RF降低到了0.196。
