Vasudeva Bhavya, Deora Puneesh, Pradhan Pradhan Mohan, Dasgupta Sudeb
Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Uttarakhand, India.
Healthc Technol Lett. 2020 Nov 13;7(5):125-131. doi: 10.1049/htl.2020.0016. eCollection 2020 Oct.
In this Letter, the field programmable gate array (FPGA) implementation of a foetal heart rate (FHR) monitoring system is presented. The system comprises a preprocessing unit to remove various types of noise, followed by a foetal electrocardiogram (FECG) extraction unit and an FHR detection unit. To improve the precision and accuracy of the arithmetic operations, a floating-point unit is developed. A least mean squares algorithm-based adaptive filter (LMS-AF) is used for FECG extraction. Two different architectures, namely series and parallel, are proposed for the LMS-AF, with the series architecture targeting lower utilisation of hardware resources, and the parallel architecture enabling less convergence time and lower power consumption. The results show that it effectively detects the R peaks in the extracted FECG with a sensitivity of 95.74-100% and a specificity of 100%. The parallel architecture shows up to an 85.88% reduction in the convergence time for non-invasive FECG databases while the series architecture shows a 27.41% reduction in the number of flip flops used when compared with the existing FPGA implementations of various FECG extraction methods. It also shows an increase of 2-7.51% in accuracy when compared to previous works.
在这封信中，介绍了一种胎儿心率（FHR）监测系统的现场可编程门阵列（FPGA）实现。该系统包括一个用于去除各种类型噪声的预处理单元，随后是一个胎儿心电图（FECG）提取单元和一个FHR检测单元。为了提高算术运算的精度和准确性，开发了一个浮点单元。基于最小均方算法的自适应滤波器（LMS-AF）用于FECG提取。针对LMS-AF提出了两种不同的架构，即串行和并行架构，串行架构旨在降低硬件资源利用率，并行架构能够减少收敛时间并降低功耗。结果表明，它能有效检测提取的FECG中的R波峰，灵敏度为95.74 - 100%，特异性为100%。与各种FECG提取方法的现有FPGA实现相比，并行架构在无创FECG数据库中的收敛时间最多减少85.88%，而串行架构在使用的触发器数量上减少27.41%。与之前的工作相比，其准确性也提高了2 - 7.51%。
