IEEE Trans Biomed Circuits Syst. 2021 Apr;15(2):199-209. doi: 10.1109/TBCAS.2021.3062632. Epub 2021 May 25.
The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2-order hybrid-CTDT Δ∑-∑ modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional Δ∑ modulator, while employing an extra ∑-stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18-μm CMOS process and achieves a peak SNR of 105.6 dB and a dynamic range of 108.3 dB, for a maximum input range of 720 mV. The measured input-referred noise is 0.98 μV over a bandwidth of 0.5-100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts.
使用脑电图 (EEG) 和心电图 (ECG) 等技术记录生物电位信号，对前端读出电路的设计提出了重要挑战，包括噪声、电极直流偏移消除和运动伪影容限。在本文中，我们提出了一种二阶混合 CTDT Δ∑-∑调制器前端架构，通过利用传统 Δ∑调制器的过采样和噪声整形特性，同时在反馈环路中增加一个 ∑-级来消除电极直流偏移并适应运动伪影，从而应对这些挑战。为了满足该应用的严格噪声要求，位于调制器环路前向路径中的电容耦合斩波稳定放大器同时充当输入级和有源加法器。该直接数字前端芯片的原型采用标准 0.18-μm CMOS 工艺制造，在最大输入范围为 720 mV 时，可实现 105.6 dB 的峰值 SNR 和 108.3 dB 的动态范围。在 0.5-100 Hz 的带宽内，测量到的输入参考噪声为 0.98 μV，测量到的 CMRR 大于 100 dB。在人体受试者的 ECG 和 EEG 测量中，该架构能够在存在大运动伪影的情况下获取生物电位信号。
