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高速真随机数生成器的高效 FPGA 实现。

Efficient FPGA implementation of high-speed true random number generator.

机构信息

State Key Laboratory of Quantum Optics and Quantum Optics Devices, Institute of Opto-Electronics, Shanxi University, Taiyuan 030006, China and Collaborative Innovation Center of Extreme Optics, Shanxi University, Taiyuan 030006, China.

出版信息

Rev Sci Instrum. 2021 Feb 1;92(2):024706. doi: 10.1063/5.0035519.

DOI:10.1063/5.0035519
PMID:33648150
Abstract

High-speed true random number generator is a building block in the modern information security system. We propose and demonstrate an efficient high-speed true random number generator based on multiple parallel self-timed rings (STRs). To improve the security, we evaluate the randomness of the entropy source by min-entropy and exploit the information-theoretically provable Toeplitz-hashing extractor. To minimize the consumption of hardware resources of a field programmable gate array at a predetermined high throughput and maximize the throughput with the limited hardware resources, we systematically derive and investigate the dependence of the data throughput and the total consumed resources of the random number generator on the system parameters. On this basis, we make a joint optimization for the degree of parallelism of the STRs and the extraction efficiency of the extractor. A 10-Gbps true random number generator is implemented efficiently, so that the output random bits can pass all the National Institute of Standards and Technology (NIST) and Dieharder test suites.

摘要

高速真随机数生成器是现代信息安全系统的基础模块。我们提出并展示了一种基于多个并行自定时环(STR)的高效高速真随机数生成器。为了提高安全性,我们通过最小熵评估熵源的随机性,并利用信息理论上可证明的托普利兹哈希提取器。为了在预定的高数据吞吐量下最小化现场可编程门阵列的硬件资源消耗,并在有限的硬件资源下最大化吞吐量,我们系统地推导和研究了随机数发生器的数据吞吐量和总消耗资源与系统参数的依赖性。在此基础上,我们对 STR 的并行度和提取器的提取效率进行联合优化。高效地实现了 10Gbps 的真随机数生成器,使得输出的随机位能够通过所有美国国家标准与技术研究院(NIST)和 Dieharder 测试套件。

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