Baldanzi Luca, Crocetti Luca, Falaschi Francesco, Bertolucci Matteo, Belli Jacopo, Fanucci Luca, Saponara Sergio
Department of Information Engineering, University of Pisa, Via G. Caruso n. 16, 56122 Pisa, Italy.
Sensors (Basel). 2020 Mar 27;20(7):1869. doi: 10.3390/s20071869.
In the context of growing the adoption of advanced sensors and systems for active vehicle safety and driver assistance, an increasingly important issue is the security of the information exchanged between the different sub-systems of the vehicle. Random number generation is crucial in modern encryption and security applications as it is a critical task from the point of view of the robustness of the security chain. Random numbers are in fact used to generate the encryption keys to be used for ciphers. Consequently, any weakness in the key generation process can potentially leak information that can be used to breach even the strongest cipher. This paper presents the architecture of a high performance Random Number Generator (RNG) IP-core, in particular a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core, a digital hardware accelerator for random numbers generation which can be employed for cryptographically secure applications. The specifications used to develop the proposed project were derived from dedicated literature and standards. Subsequently, specific architecture optimizations were studied to achieve better timing performance and very high throughput values. The IP-core has been validated thanks to the official NIST Statistical Test Suite, in order to evaluate the degree of randomness of the numbers generated in output. Finally the CSPRNG IP-core has been characterized on relevant Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies.
在越来越多的车辆采用先进传感器和系统以实现主动车辆安全和驾驶员辅助功能的背景下，一个日益重要的问题是车辆不同子系统之间交换信息的安全性。随机数生成在现代加密和安全应用中至关重要，因为从安全链的稳健性角度来看，它是一项关键任务。实际上，随机数用于生成用于密码的加密密钥。因此，密钥生成过程中的任何弱点都可能潜在地泄露可用于破解即使是最强密码的信息。本文介绍了一种高性能随机数发生器（RNG）IP核的架构，特别是一种密码学安全伪随机数发生器（CSPRNG）IP核，这是一种用于随机数生成的数字硬件加速器，可用于密码学安全应用。用于开发所提出项目的规范源自专门的文献和标准。随后，研究了特定的架构优化以实现更好的时序性能和非常高的吞吐量值。借助官方的美国国家标准与技术研究院（NIST）统计测试套件对该IP核进行了验证，以评估输出生成数字的随机程度。最后，在相关的现场可编程门阵列（FPGA）和专用集成电路（ASIC）标准单元技术上对CSPRNG IP核进行了特性分析。
