Gomez-Rodriguez Jose Ricardo, Sandoval-Arechiga Remberto, Ibarra-Delgado Salvador, Rodriguez-Abdala Viktor Ivan, Vazquez-Avila Jose Luis, Parra-Michel Ramon
Academic Unit of Electrical Engineering, Center of Research, Innovation and Development in Telecommunications (CIDTE), Autonomous University of Zacatecas, Zacatecas 98000, Mexico.
Department of Electronic and Computer Engineering, University of Cordoba, 14071 Córdoba, Spain.
Micromachines (Basel). 2021 Feb 12;12(2):183. doi: 10.3390/mi12020183.
Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs-optimized and fixed at synthesis time-the interconnection nonconformity with the different applications' requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.
当前的计算平台鼓励将数千个处理核心及其互连集成到单个芯片中。移动智能手机、物联网、嵌入式设备、台式机和数据中心使用多核片上系统（SoC）来利用其计算能力和并行性，以满足动态工作负载需求。片上网络（NoC）为具有不同流量模式和数据依赖性的各种应用带来了可扩展的连接性。然而，当系统在传统的、在合成时进行优化和固定的NoC中执行各种应用时，互连与不同应用需求的不一致会在性能上产生限制。在文献中，NoC设计采用了软件定义网络（SDN）策略，以演变成未来芯片的一种适应性互连解决方案。然而，所调查的工作采用了部分软件定义片上网络（SDNoC）方法，忽略了在传统网络中带来互操作性的SDN分层架构。本文探索了SDNoC文献，并根据每项工作所呈现的期望SDN特性对其进行分类。然后，我们描述了从文献调查中发现的挑战和机遇。此外，我们解释了采用SDNoC方法的动机，并阐述了SDN和SDNoC的概念及架构。我们观察到文献中的工作采用了不完整的分层SDNoC方法。这一事实在SDNoC架构中创造了多个研究人员可为多核SoC设计做出贡献的丰富领域。
