Bazzi Hiba S, Jaber Ramzi A, El-Hajj Ahmad M, Hija Fathelalem A, Haidar Ali M
Electrical and Computer Engineering Department, Beirut Arab University, Debieh 1504, Lebanon.
Electrical and Electronic Engineering Department, Lebanese University, Hadath 40016, Lebanon.
Micromachines (Basel). 2024 Jul 31;15(8):997. doi: 10.3390/mi15080997.
Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.
软件定义网络（SDN）通过将控制平面功能与数据平面设备解耦，彻底改变了网络管理方式，实现了网络行为的集中控制和可编程性。本文使用三进制系统来改进SDN控制器内部的中央处理器（CPU），以增强网络管理能力。与二进制电路相比，多值逻辑（MVL）电路在芯片面积、传播延迟和能耗方面有显著改进。此外，与其他晶体管技术相比，碳纳米管场效应晶体管（CNTFET）在能源效率和电路速度方面有所提升。据我们所知，这是首次在SDN控制器的CPU内部应用三进制设计。早期研究主要集中在SDN中的三态内容可寻址存储器（TCAM）。本文提出了一种新的1三进制三进制全加器（TFA），以减少传播延迟和功率延迟积（PDP）。使用HSPICE模拟器，将所提出的设计与最新的17种设计进行比较，其中包括15种基于1三进制TFA CNTFET的设计、2种基于2位二进制FA FinFET的设计和2种基于2位二进制FA CMOS的设计，以优化SDN环境中的CPU利用率，从而提高可编程性。结果表明，与基于2位二进制FA CMOS的设计相比，所提出的设计成功地将传播延迟降低了99%以上；与基于2位二进制FA FinFET的设计相比，降低了78%以上；与最坏情况的TFA相比，降低了91%以上；与最佳情况的TFA相比，降低了49%以上。
