Department of Biomedical Engineering, School of Medicine, Kyungpook National University, Daegu, Korea.
Gyeongbuk Branch Office, Korea Testing Certification, Daegu, Korea.
Technol Health Care. 2021;29(S1):399-413. doi: 10.3233/THC-218038.
Recently, with the increase in the population of hearing impaired people, various types of hearing aids have been rapidly developed. In particular, a fully implantable middle ear hearing device (F-IMEHD) is developed for people with sensorineural hearing loss. The F-IMEHD system comprises an implantable microphone, a transducer, and a signal processor. The signal processor should have a small size and consume less power for implantation in a human body.
In this study, we designed and fabricated a signal-processing chip using the modified FFT algorithm. This algorithm was developed focusing on eliminating time delay and system complexity in the transform process. The designed signal-processing chip comprises a 4-channel WDRC, a fitting memory, a communication 1control part, and a pulse density modulator. Each channel is separated using a 64-point fast Fourier transform (FFT) method and the gain value is matched using the fitting table in the fitting memory.
The chip was designed by Verilog-HDL and the designed HDL codes were verified by Modelsim-PE 10.3 (Mentor graphics, USA). The chip was fabricated using a 0.18 μm CMOS process (SMIC, China). Experiments were performed on a cadaver to verify the performance of the fabricated chip.
近年来，随着听力受损人群的增加，各种类型的助听器得到了迅速发展。特别是，为感音神经性听力损失患者开发了全植入式中耳听力设备（F-IMEHD）。F-IMEHD 系统包括植入式麦克风、换能器和信号处理器。信号处理器应为植入人体时体积小、功耗低。
在这项研究中，我们使用改进的 FFT 算法设计和制造了一个信号处理芯片。该算法的开发重点是消除转换过程中的时滞和系统复杂性。设计的信号处理芯片包括 4 个通道的 WDRC、拟合存储器、通信控制部分和脉冲密度调制器。每个通道使用 64 点快速傅里叶变换（FFT）方法进行分离，并使用拟合存储器中的拟合表匹配增益值。
该芯片使用 Verilog-HDL 进行设计，使用 Modelsim-PE 10.3（Mentor graphics，USA）对设计的 HDL 代码进行验证。该芯片使用 0.18 μm CMOS 工艺（SMIC，中国）进行制造。在尸体上进行了实验以验证所制造芯片的性能。
