Lee Khwang-Sun, Park Jun-Young
School of Electronics Engineering, Chungbuk National University, Cheongju 28644, Korea.
Micromachines (Basel). 2022 Mar 11;13(3):432. doi: 10.3390/mi13030432.
This paper proposes a simplified fabrication processing for nanosheet Field-Effect Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane (GP) region can be replaced by an epitaxial grown doped ultra-thin (DUT) layer on the starting wafer prior to Si/SiGe stack formation. The proposed process flow can be performed in-situ, and does not require changing chambers or a high temperature annealing process. In short, conventional processes such as ion implantation and subsequent thermal annealing, which have been utilized for the GP region, can be replaced without degrading device performance.
本文提出了一种用于3纳米以上节点技术的纳米片场效应晶体管（FET）的简化制造工艺。接地平面（GP）区域的形成可以通过在形成Si/SiGe堆叠之前在起始晶圆上外延生长掺杂超薄（DUT）层来替代。所提出的工艺流程可以原位进行，并且不需要更换腔室或进行高温退火工艺。简而言之，用于GP区域的诸如离子注入和随后的热退火等传统工艺可以被替代，而不会降低器件性能。
