Cao Yue, Guo Shuchen, Jiang Shuai, Zhou Xuan, Wang Xiaobei, Luo Yunhua, Yu Zhongjun, Zhang Zhimin, Deng Yunkai
Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100094, China.
School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing 101408, China.
Sensors (Basel). 2022 Mar 16;22(6):2292. doi: 10.3390/s22062292.
This study conducts an in-depth evaluation of imaging algorithms and software and hardware architectures to meet the capability requirements of real-time image acquisition systems, such as spaceborne and airborne synthetic aperture radar (SAR) systems. By analysing the principles and models of SAR imaging, this research creatively puts forward the fully parallel processing architecture for the back projection (BP) algorithm based on Field-Programmable Gate Array (FPGA). The processing time consumption has significant advantages compared with existing methods. This article describes the BP imaging algorithm, which stands out with its high processing accuracy and two-dimensional decoupling of distance and azimuth, and analyses the algorithmic flow, operation, and storage requirements. The algorithm is divided into five core operations: range pulse compression, upsampling, oblique distance calculation, data reading, and phase accumulation. The architecture and optimisation of the algorithm are presented, and the optimisation methods are described in detail from the perspective of algorithm flow, fixed-point operation, parallel processing, and distributed storage. Next, the maximum resource utilisation rate of the hardware platform in this study is found to be more than 80%, the system power consumption is 21.073 W, and the processing time efficiency is better than designs with other FPGA, DSP, GPU, and CPU. Finally, the correctness of the processing results is verified using actual data. The experimental results showed that 1.1 s were required to generate an image with a size of 900 × 900 pixels at a 200 MHz clock rate. This technology can solve the multi-mode, multi-resolution, and multi-geometry signal processing problems in an integrated manner, thus laying a foundation for the development of a new, high-performance, SAR system for real-time imaging processing.
本研究对成像算法以及软件和硬件架构进行了深入评估，以满足诸如星载和机载合成孔径雷达（SAR）系统等实时图像采集系统的性能要求。通过分析SAR成像的原理和模型，本研究创新性地提出了基于现场可编程门阵列（FPGA）的用于后向投影（BP）算法的全并行处理架构。与现有方法相比，其处理时间消耗具有显著优势。本文介绍了BP成像算法，该算法以其高处理精度以及距离和方位的二维解耦脱颖而出，并分析了算法流程、操作和存储要求。该算法分为五个核心操作：距离脉冲压缩、上采样、斜距计算、数据读取和相位积累。文中给出了该算法的架构和优化，并从算法流程、定点运算、并行处理和分布式存储的角度详细描述了优化方法。接下来，本研究发现硬件平台的最大资源利用率超过80%，系统功耗为21.073 W，处理时间效率优于其他采用FPGA、DSP、GPU和CPU的设计。最后，使用实际数据验证了处理结果的正确性。实验结果表明，在200 MHz时钟速率下生成一幅900×900像素大小的图像需要1.1 s。该技术能够以集成方式解决多模式、多分辨率和多几何信号处理问题，从而为开发新型高性能实时成像处理SAR系统奠定基础。
