School of Electronics and Information Engineering, Korea Aerospace University, Goyang-si 10540, Republic of Korea.
Department of Smart Air Mobility, Korea Aerospace University, Goyang-si 10540, Republic of Korea.
Sensors (Basel). 2023 Jan 14;23(2):959. doi: 10.3390/s23020959.
Synthetic aperture radar (SAR), which can generate images of regions or objects, is an important research area of radar. The chirp scaling algorithm (CSA) is a representative SAR imaging algorithm. The CSA has a simple structure comprising phase compensation and fast Fourier transform (FFT) operations by replacing interpolation for range cell migration correction (RCMC) with phase compensation. However, real-time processing still requires many computations and a long execution time. Therefore, it is necessary to develop a hardware accelerator to improve the speed of algorithm processing. In addition, the demand for a small SAR system that can be mounted on a small aircraft or drone and that satisfies the constraints of area and power consumption is increasing. In this study, we proposed a CSA-based SAR processor that supports FFT and phase compensation operations and presents field-programmable gate array (FPGA)-based implementation results. We also proposed a modified CSA flow that simplifies the traditional CSA flow by changing the order in which the transpose operation occurs. Therefore, the proposed CSA-based SAR processor was designed to be suitable for modified CSA flow. We designed the multiplier for FFT to be shared for phase compensation, thereby achieving area efficiency and simplifying the data flow. The proposed CSA-based SAR processor was implemented on a Xilinx UltraScale+ MPSoC FPGA device and designed using Verilog-HDL. After comparing the execution times of the proposed SAR processor and the ARM cortex-A53 microprocessor, we observed a 136.2-fold increase in speed for the 4096 × 4096-pixel image.
合成孔径雷达（SAR）可以生成区域或物体的图像，是雷达的一个重要研究领域。线性调频斜率算法（CSA）是一种典型的 SAR 成像算法。CSA 具有简单的结构，包括相位补偿和快速傅里叶变换（FFT）操作，通过用相位补偿代替距离单元徙动校正（RCMC）的插值来实现。然而，实时处理仍然需要大量的计算和较长的执行时间。因此，需要开发硬件加速器来提高算法处理速度。此外，对能够安装在小型飞机或无人机上且满足面积和功耗限制的小型 SAR 系统的需求也在不断增加。在本研究中，我们提出了一种基于 CSA 的 SAR 处理器，该处理器支持 FFT 和相位补偿操作，并给出了基于现场可编程门阵列（FPGA）的实现结果。我们还提出了一种修改后的 CSA 流，通过改变转置操作的顺序来简化传统的 CSA 流。因此，所提出的基于 CSA 的 SAR 处理器被设计为适合修改后的 CSA 流。我们设计了用于 FFT 的乘法器来共享相位补偿，从而实现了面积效率和简化了数据流。所提出的基于 CSA 的 SAR 处理器是在 Xilinx UltraScale+MPSoC FPGA 器件上实现的，并使用 Verilog-HDL 进行设计。在比较了所提出的 SAR 处理器和 ARM cortex-A53 微处理器的执行时间后，我们观察到对于 4096×4096 像素的图像，速度提高了 136.2 倍。
