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一种基于科尔德科算法的高精度、节能型伊兹海克维奇神经元,具有误差抑制与补偿功能。

A High-Accuracy and Energy-Efficient CORDIC Based Izhikevich Neuron With Error Suppression and Compensation.

作者信息

Wang Jipeng, Peng Zixuan, Zhan Yi, Li Yujie, Yu Guoyi, Chong Kwen-Siong, Wang Chao

出版信息

IEEE Trans Biomed Circuits Syst. 2022 Oct;16(5):807-821. doi: 10.1109/TBCAS.2022.3191004. Epub 2022 Nov 30.

Abstract

Bio-inspired neuron models are the key building blocks of brain-like neural networks for brain-science exploration and neuromorphic engineering applications. The efficient hardware design of bio-inspired neuron models is one of the challenges to implement brain-like neural networks, as the balancing of model accuracy, energy consumption and hardware cost is very challenging. This paper proposes a high-accuracy and energy-efficient Fast-Convergence COordinate Rotation DIgital Computer (FC-CORDIC) based Izhikevich neuron design. For ensuring the model accuracy, an error propagation model of the Izhikevich neuron is presented for systematic error analysis and effective error reduction. Parameter-Tuning Error Compensation (PTEC) method and Bitwidth-Extension Error Suppression (BEES) method are proposed to reduce the error of Izhikevich neuron design effectively. In addition, by utilizing the FC-CORDIC instead of conventional CORDIC for square calculation in the Izhikevich model, the redundant CORDIC iterations are removed and therefore, both the accumulated errors and required computation are effectively reduced, which significantly improve the accuracy and energy efficiency. An optimized fixed-point design of FC-CORDIC is also proposed to save hardware overhead while ensuring the accuracy. FPGA implementation results exhibit that the proposed Izhikevich neuron design can achieve high accuracy and energy efficiency with an acceptable hardware overhead, among the state-of-the-art designs.

摘要

受生物启发的神经元模型是用于脑科学探索和神经形态工程应用的类脑神经网络的关键构建模块。受生物启发的神经元模型的高效硬件设计是实现类脑神经网络的挑战之一,因为在模型准确性、能耗和硬件成本之间取得平衡极具挑战性。本文提出了一种基于高精度、高能效的快速收敛坐标旋转数字计算机(FC-CORDIC)的Izhikevich神经元设计。为确保模型准确性,提出了Izhikevich神经元的误差传播模型,用于系统误差分析和有效误差降低。提出了参数调整误差补偿(PTEC)方法和位宽扩展误差抑制(BEES)方法,以有效降低Izhikevich神经元设计的误差。此外,通过在Izhikevich模型中使用FC-CORDIC代替传统的CORDIC进行平方计算,消除了冗余的CORDIC迭代,从而有效减少了累积误差和所需计算量,显著提高了准确性和能效。还提出了一种优化的FC-CORDIC定点设计,以在确保准确性的同时节省硬件开销。现场可编程门阵列(FPGA)实现结果表明,在所提出的Izhikevich神经元设计在现有最先进设计中,能够在可接受的硬件开销下实现高精度和高能效。

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