Haggui Naouel, Hamidouche Wassim, Belghith Fatma, Masmoudi Nouri, Nezan Jean-François
Univ Rennes, INSA Rennes, CNRS, IETR - UMR 6164, Rennes, 20 Avenue des Buttes de Coesmes, Rennes, 35700 France.
Electronics and Information Technology Laboratory (LETI) of Sfax, Road of Soukra, Sfax, 3038 Tunisia.
J Signal Process Syst. 2022 Oct 14:1-13. doi: 10.1007/s11265-022-01819-7.
The emergence of the new video coding standard, Versatile Video Coding (VVC), has resulted in a 40-50% coding gain over its predecessor HEVC for the same visual quality. However, this is accompanied by a sharp increase in computational complexity. The emergence of the VVC standard and the increase in video resolution have exceeded the capacity of single-core architectures. This fact has led researchers to use multicore architectures for the implementation of video standards and to use the parallelism of these architectures for real-time applications. With the strong growth in both areas, video coding and multicore architecture, there is a great need for a design methodology that facilitates the exploration of heterogeneous multicore architectures, which automatically generates optimized code for these architectures in order to reduce time to market. In this context, this paper aims to use the methodology based on data flow modeling associated with the PREESM software. This paper shows how the software has been used to model a complete standard VVC video decoder using Parameterized and Interfaced Synchronous Dataflow (PiSDF) model. The proposed model takes advantage of the parallelism strategies of the OpenVVC decoder and in particular the tile-based parallelism. Experimental results show that the speed of the VVC decoder in PiSDF is slightly higher than the OpenVVC decoder handwritten in C/C++ languages, by up to 11% speedup on a 24-core processor. Thus, the proposed decoder outperforms the state-of-the-art dataflow decoders based on the RVC-CAL model.
新型视频编码标准通用视频编码（VVC）的出现，使得在相同视觉质量下，相较于其前身高效视频编码（HEVC），编码增益提高了40%-50%。然而，这伴随着计算复杂度的急剧增加。VVC标准的出现以及视频分辨率的提高已经超出了单核架构的能力。这一事实促使研究人员使用多核架构来实现视频标准，并利用这些架构的并行性来进行实时应用。随着视频编码和多核架构这两个领域的强劲发展，迫切需要一种设计方法来促进对异构多核架构的探索，该方法能自动为这些架构生成优化代码，以缩短上市时间。在此背景下，本文旨在使用基于与PREESM软件相关联的数据流建模的方法。本文展示了该软件如何被用于使用参数化接口同步数据流（PiSDF）模型对完整的标准VVC视频解码器进行建模。所提出的模型利用了OpenVVC解码器的并行策略，特别是基于切片的并行性。实验结果表明，PiSDF中VVC解码器的速度略高于用C/C++语言手写的OpenVVC解码器，在24核处理器上加速比高达11%。因此，所提出的解码器优于基于RVC-CAL模型的现有数据流解码器。
