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FPGA 实现雷达系统中的高效 CFAR 算法。

FPGA Implementation of Efficient CFAR Algorithm for Radar Systems.

机构信息

School of Electronics and Information Engineering, Korea Aerospace University, Goyang-si 10540, Republic of Korea.

Department of Smart Air Mobility, Korea Aerospace University, Goyang-si 10540, Republic of Korea.

出版信息

Sensors (Basel). 2023 Jan 13;23(2):954. doi: 10.3390/s23020954.

DOI:10.3390/s23020954
PMID:36679752
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC9861839/
Abstract

The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 μs to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation.

摘要

恒虚警率(CFAR)算法在雷达信号处理中对目标检测至关重要。它已经得到了改进,可以更准确地检测目标,特别是在非均匀环境中,如多目标或杂波边缘环境。例如,有基于排序的和基于变量索引的算法。然而,这些算法需要大量的计算,因此很难应用于需要实时目标检测的雷达应用中。我们提出了一种新的 CFAR 算法,该算法通过新的决策准则来确定接收信号的环境,并应用最优的 CFAR 算法,如改进的变量索引(MVI)和基于自动屏蔽单元平均的有序数据变化(ACCA-ODV)。所提出的 CFAR 算法的蒙特卡罗模拟结果表明,在基于 SNR 为 25dB 的均匀和非均匀环境下,具有 93.8%的高检测概率。此外,本文提出了该算法的硬件设计、基于现场可编程门阵列(FPGA)的实现和实际应用的验证结果。我们通过分时求和和平方运算以及用乘法运算代替除法运算来减少硬件复杂度,在计算决策参数时。我们还开发了一种低复杂度和高速排序器架构,用于对前导和滞后窗口中的部分数据进行排序。因此,该实现使用了 8260 个 LUT 和 3823 个寄存器,操作时间为 0.6μs。与之前提出的 FPGA 实现结果相比,证实了所提出的 CFAR 处理器的复杂性和操作速度非常适合实时实现。

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本文引用的文献

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