Departamento de Informática e Ingeniería de Sistemas - Aragón Institute for Engineering Research (I3A), Universidad de Zaragoza, Zaragoza, Spain.
Department of Electronic Engineering and Communications, I3A, Universidad de Zaragoza, Zaragoza, Spain.
PLoS One. 2023 Feb 7;18(2):e0278346. doi: 10.1371/journal.pone.0278346. eCollection 2023.
Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the bitcells to the point of eventually losing their storage capacity. In this context, this paper presents a novel LLC organization designed to extend the lifetime of the NV data array and a procedure to forecast in detail the capacity and performance of such an NV-LLC over its lifetime. From a methodological point of view, although different approaches are used in the literature to analyze the degradation of an NV-LLC, none of them allows to study in detail its temporal evolution. In this sense, this work proposes a forecasting procedure that combines detailed simulation and prediction, allowing an accurate analysis of the impact of different cache control policies and mechanisms (replacement, wear-leveling, compression, etc.) on the temporal evolution of the indices of interest, such as the effective capacity of the NV-LLC or the system IPC. We also introduce L2C2, a LLC design intended for implementation in NV memory technology that combines fault tolerance, compression, and internal write wear leveling for the first time. Compression is not used to store more blocks and increase the hit rate, but to reduce the write rate and increase the lifetime during which the cache supports near-peak performance. In addition, to support byte loss without performance drop, L2C2 inherently allows N redundant bytes to be added to each cache entry. Thus, L2C2+N, the endurance-scaled version of L2C2, allows balancing the cost of redundant capacity with the benefit of longer lifetime. For instance, as a use case, we have implemented the L2C2 cache with STT-RAM technology. It has affordable hardware overheads compared to that of a baseline NV-LLC without compression in terms of area, latency and energy consumption, and increases up to 6-37 times the time in which 50% of the effective capacity is degraded, depending on the variability in the manufacturing process. Compared to L2C2, L2C2+6 which adds 6 bytes of redundant capacity per entry, that means 9.1% of storage overhead, can increase up to 1.4-4.3 times the time in which the system gets its initial peak performance degraded.
几种新兴的非易失性 (NV) 存储技术作为构建最后一级高速缓存 (LLC) 的替代方案而备受关注。与 SRAM 相比，它们的优势在于更高的密度和更低的静态功耗，但写入操作会磨损位单元，最终导致其存储容量丢失。在这种情况下，本文提出了一种新颖的 LLC 组织，旨在延长 NV 数据阵列的寿命，并详细介绍了一种预测这种 NV-LLC 在其寿命内的容量和性能的方法。从方法学的角度来看，尽管文献中使用了不同的方法来分析 NV-LLC 的退化，但没有一种方法可以详细研究其时间演变。在这方面，这项工作提出了一种预测程序，它结合了详细的模拟和预测，允许对不同的缓存控制策略和机制（替换、磨损均衡、压缩等）对感兴趣的指标的时间演变的影响进行精确分析，例如 NV-LLC 的有效容量或系统 IPC。我们还引入了 L2C2，这是一种旨在在 NV 存储技术中实现的 LLC 设计，它首次结合了容错性、压缩和内部写入磨损均衡。压缩不是用于存储更多块和提高命中率，而是用于降低写入率并延长缓存支持接近峰值性能的时间。此外，为了支持字节丢失而不降低性能，L2C2 允许在每个缓存项中添加 N 个冗余字节。因此，L2C2+N，即 L2C2 的耐用性扩展版本，允许在冗余容量的成本与更长寿命的收益之间取得平衡。例如，作为一个用例，我们使用 STT-RAM 技术实现了 L2C2 缓存。与没有压缩的基准 NV-LLC 相比，它在面积、延迟和能耗方面具有可承受的硬件开销，并且根据制造过程的变化，有效容量降低 50%的时间可以延长 6-37 倍。与 L2C2 相比，添加每个项 6 个字节冗余容量的 L2C2+6（意味着 9.1%的存储开销）可以将系统初始峰值性能降低的时间延长 1.4-4.3 倍。
