Poongan Balamahesn, Rajendran Jagadheswaran, Yizhi Li, Mariappan Selvakumar, Parameswaran Pharveen, Kumar Narendra, Othman Masuri, Nathan Arokia
Collaborative Microelectronic Design Excellence Center (CEDEC), Universiti Sains Malaysia, Bayan Lepas 11900, Penang, Malaysia.
Department of Electrical Engineering, Faculty of Engineering, University of Malaya, Kuala Lumpur 50603, Wilayah Persekutuan, Malaysia.
Micromachines (Basel). 2023 Feb 2;14(2):379. doi: 10.3390/mi14020379.
A low-power capacitorless demultiplexer-based multi-voltage domain low-dropout regulator (MVD-LDO) with 180 nm CMOS technology is proposed in this work. The MVD-LDO has a 1.5 V supply voltage headroom and regulates an output from four voltage domains ranging from 0.8 V to 1.4 V, with a high current efficiency of 99.98% with quiescent current of 53 µA with the aid of an integrated low-power demultiplexer controller which consumes only 68.85 pW. The fabricated chip has an area of 0.149 mm and can deliver up to 400 mA of current. The MVD-LDO's line and load regulations are 1.85 mV/V and 0.0003 mV/mA for the low-output voltage domain and 3.53 mV/V and 0.079 mV/mA for the high-output voltage domain. The LDO consumes only 174.5 µW in standby mode, making it suitable for integrating with an RF energy harvester chip to power sensor nodes.
本文提出了一种采用180纳米CMOS技术、基于低功耗无电容解复用器的多电压域低压差稳压器(MVD-LDO)。该MVD-LDO具有1.5V的电源电压裕量,可调节来自四个电压域的输出,电压范围为0.8V至1.4V,借助仅消耗68.85 pW的集成低功耗解复用器控制器,静态电流为53μA时,电流效率高达99.98%。所制造芯片的面积为0.149平方毫米,可提供高达400mA的电流。对于低输出电压域,MVD-LDO的线性调节和负载调节分别为1.85mV/V和0.0003mV/mA;对于高输出电压域,分别为3.53mV/V和0.079mV/mA。该LDO在待机模式下仅消耗174.5μW,适用于与射频能量采集芯片集成,为传感器节点供电。