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基于垂直交叉阵列结构中铝掺杂自整流忆阻器的高度并行有状态布尔逻辑门。

Highly parallel stateful Boolean logic gates based on aluminum-doped self-rectifying memristors in a vertical crossbar array structure.

作者信息

Park Taegyun, Kim Seung Soo, Lee Byeol Jun, Park Tae Won, Kim Hae Jin, Hwang Cheol Seong

机构信息

Department of Materials Science and Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul 08826, Republic of Korea.

Department of Materials Science and Engineering, Myongji University, Yongin, 17058, Republic of Korea.

出版信息

Nanoscale. 2023 Mar 30;15(13):6387-6395. doi: 10.1039/d3nr00271c.

DOI:10.1039/d3nr00271c
PMID:36919469
Abstract

The self-rectifying memristor with electronic bipolar resistive switching shows electroforming-free, highly rectifying properties and low operating power. Furthermore, configuring the memristors in a vertical array structure provides a higher memory density than in a planar array structure. These combined advantages can be exploited in in-memory computing, which may provide a new and efficient stateful logic gate with high parallelism compared to the conventional stateful logic gates in the planar array structure. The different switching mechanism compared to the previous logic gates based on filamentary-type switching is explained and exploited to realize the AND and OR Boolean logic gates. Since the AND and OR logic functions are the basic operations of sum-of-product (SoP) and product-of-sum (PoS) expressions, any canonical expression for Boolean logic can be implemented in the vertical crossbar array (CBA). Accordingly, the composite logic gate, such as an exclusive OR operation, is demonstrated. In addition, the implementation of the memristive priority encoder is proposed using parallel logic gates. Although the switching speed should be improved in further work, a higher parallelism with a larger number of layers in the vertical array structure can mitigate the low operation speed issue.

摘要

具有电子双极电阻开关的自整流忆阻器表现出无电形成、高度整流特性和低工作功耗。此外,将忆阻器配置为垂直阵列结构比平面阵列结构具有更高的存储密度。这些综合优势可用于内存计算,与平面阵列结构中的传统状态逻辑门相比,内存计算可以提供一种具有高并行度的新型高效状态逻辑门。解释并利用了与基于丝状开关的先前逻辑门不同的开关机制,以实现与门和或门布尔逻辑门。由于与门和或门逻辑功能是积之和(SoP)和和之积(PoS)表达式的基本运算,因此布尔逻辑的任何规范表达式都可以在垂直交叉点阵列(CBA)中实现。相应地,展示了复合逻辑门,如异或运算。此外,还提出了使用并行逻辑门实现忆阻优先编码器。尽管在进一步的工作中应提高开关速度,但垂直阵列结构中更多层数的更高并行度可以缓解低运算速度问题。

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