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基于 TaO 双层的忆阻器实现三进制状态的带状态的神经网络的三进制逻辑。

Ternary Logic with Stateful Neural Networks Using a Bilayered TaO -Based Memristor Exhibiting Ternary States.

机构信息

Department of Materials Science and Engineering, KAIST, 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Republic of Korea.

出版信息

Adv Sci (Weinh). 2022 Feb;9(5):e2104107. doi: 10.1002/advs.202104107. Epub 2021 Dec 16.

Abstract

A memristive stateful neural network allowing complete Boolean in-memory computing attracts high interest in future electronics. Various Boolean logic gates and functions demonstrated so far confirm their practical potential as an emerging computing device. However, spatio-temporal efficiency of the stateful logic is still too limited to replace conventional computing technologies. This study proposes a ternary-state memristor device (simply a ternary memristor) for application to ternary stateful logic. The ternary-state implementable memristor device is developed with bilayered tantalum oxide by precisely controlling the oxygen content in each oxide layer. The device can operate 157 ternary logic gates in one operational clock, which allows an experimental demonstration of a functionally complete three-valued Łukasiewicz logic system. An optimized logic cascading strategy with possible ternary gates is ≈20% more efficient than conventional binary stateful logic, suggesting it can be beneficial for higher performance in-memory computing.

摘要

一种允许完整布尔值内存计算的忆阻状态神经网络在未来电子学中引起了高度关注。到目前为止,各种布尔逻辑门和功能的演示证实了它们作为一种新兴计算设备的实际潜力。然而,状态逻辑的时空效率仍然太低,无法替代传统的计算技术。本研究提出了一种用于三值状态逻辑的三进制忆阻器件(简称三进制忆阻器)。通过精确控制每个氧化层中的氧含量,开发出具有双层氧化钽的三进制可实现忆阻器件。该器件可以在一个工作时钟中操作 157 个三进制逻辑门,从而可以实现功能完备的三值Łukasiewicz 逻辑系统的实验演示。具有可能的三进制门的优化逻辑级联策略比传统的二进制状态逻辑效率提高约 20%,这表明它有助于提高内存计算的性能。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5685/8844464/8031e9c16c6e/ADVS-9-2104107-g001.jpg

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