Department of Microelectronic Science and Engineering School of Physical Science and Technology, Ningbo University, Fenghua Road 818, Ningbo 315211, China.
National Laboratory of Solid State Microstructures, Nanjing University, Nanjing 210093, China.
Phys Chem Chem Phys. 2023 Mar 29;25(13):9413-9427. doi: 10.1039/d2cp05226a.
As a promising photovoltaic technology, halide perovskite solar cells (PSCs) have recently attracted wide attention. This work presents a systematic simulation of low bandgap formamidinium tin iodide (FASnI)-based p-n heterojunction PSCs to investigate the effects of multiple optoelectronic variations on the photovoltaic performance. The structures of the simulated devices are n-i-p, electron transport layer-free (ETL-free), hole transport layer-free (HTL-free), and inverted HTL-free. The simulation is conducted with the Solar Cell Capacitance Simulator (SCAPS-1D). The power conversion efficiencies (PCEs) dramatically decrease when the acceptor doping density () of the absorber layer exceeds 10 cm. For all devices, the photovoltaic parameters dramatically decrease when the absorber defect density () is over 10 cm, and the best absorber layer thickness is 1000 nm. It should be pointed out that the and the interface defect layer (IDL) are the primary culprits that seriously affect the device performance. When the interfacial defect density () exceeds 10 cm, PCEs begin to decline significantly. Therefore, paying attention to these defect layers is necessary to improve the PCE. Furthermore, the proper conduction band offset (CBO) between the electron transport layer (ETL) and absorber layer positively affects PSCs' performance. These simulation results help fabricate highly efficient and environment-friendly narrow bandgap PSCs.
作为一种很有前途的光伏技术，卤化物钙钛矿太阳能电池（PSC）最近引起了广泛关注。本工作对基于低带隙甲脒碘化锡（FASnI）的 p-n 异质结 PSC 进行了系统的模拟，以研究多种光电变化对光伏性能的影响。模拟器件的结构为 n-i-p、无电子传输层（ETL-free）、无空穴传输层（HTL-free）和倒置 HTL-free。模拟采用太阳能电池电容模拟器（SCAPS-1D）进行。当吸收层的受主掺杂密度（）超过 10 cm 时，功率转换效率（PCE）会急剧下降。对于所有器件，当吸收层缺陷密度（）超过 10 cm 时，光伏参数会急剧下降，最佳吸收层厚度为 1000nm。应该指出的是，和界面缺陷层（IDL）是严重影响器件性能的主要因素。当界面缺陷密度（）超过 10 cm 时，PCE 开始显著下降。因此，注意这些缺陷层对于提高 PCE 是必要的。此外，电子传输层（ETL）和吸收层之间适当的导带偏移（CBO）对 PSC 的性能有积极影响。这些模拟结果有助于制备高效、环保的窄带隙 PSC。
