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用于使用忆阻器交叉阵列对神经网络进行快速且节能训练的CMOS兼容二阶忆阻器的线性电导更新改进

Linear conductance update improvement of CMOS-compatible second-order memristors for fast and energy-efficient training of a neural network using a memristor crossbar array.

作者信息

Park See-On, Park Taehoon, Jeong Hakcheon, Hong Seokman, Seo Seokho, Kwon Yunah, Lee Jongwon, Choi Shinhyun

机构信息

The School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Republic of Korea.

Nano Convergence Technology Division, National Nanofab Center (NNFC), 291, Daehak-ro, Daejeon 34141, Republic of Korea.

出版信息

Nanoscale Horiz. 2023 Sep 26;8(10):1366-1376. doi: 10.1039/d3nh00121k.

Abstract

Memristors are two-terminal memory devices that can change the conductance state and store analog values. Thanks to their simple structure, suitability for high-density integration, and non-volatile characteristics, memristors have been intensively studied as synapses in artificial neural network systems. Memristive synapses in neural networks have theoretically better energy efficiency compared with conventional von Neumann computing processors. However, memristor crossbar array-based neural networks usually suffer from low accuracy because of the non-ideal factors of memristors such as non-linearity and asymmetry, which prevent weights from being programmed to their targeted values. In this article, the improvement in linearity and symmetry of pulse update of a fully CMOS-compatible HfO-based memristor is discussed, by using a second-order memristor effect with a heating pulse and a voltage divider composed of a series resistor and two diodes. We also demonstrate that the improved device characteristics enable energy-efficient and fast training of a memristor crossbar array-based neural network with high accuracy through a realistic model-based simulation. By improving the memristor device's linearity and symmetry, our results open up the possibility of a trainable memristor crossbar array-based neural network system that possesses great energy efficiency, high area efficiency, and high accuracy at the same time.

摘要

忆阻器是一种双端存储器件,能够改变电导状态并存储模拟值。由于其结构简单、适合高密度集成以及非易失性特性,忆阻器作为人工神经网络系统中的突触受到了广泛研究。与传统的冯·诺依曼计算处理器相比,神经网络中的忆阻突触在理论上具有更高的能量效率。然而,基于忆阻器交叉阵列的神经网络通常由于忆阻器的非线性和不对称性等非理想因素而精度较低,这些因素会阻止权重被编程到目标值。在本文中,通过使用具有加热脉冲的二阶忆阻器效应以及由串联电阻和两个二极管组成的分压器,讨论了全CMOS兼容的基于HfO的忆阻器脉冲更新的线性度和对称性的改进。我们还通过基于实际模型的仿真证明,改进后的器件特性能够实现基于忆阻器交叉阵列的神经网络的高效节能且快速的高精度训练。通过提高忆阻器器件的线性度和对称性,我们的结果为同时具备高能量效率、高面积效率和高精度的基于忆阻器交叉阵列的可训练神经网络系统开辟了可能性。

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