Li Ping, Guo Jingwei, Hu Shengdong, Lin Zhi
Chongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, China.
China Resources Microelectronics (Chongqing) Ltd., Chongqing 401331, China.
Micromachines (Basel). 2023 Jun 22;14(7):1282. doi: 10.3390/mi14071282.
A novel split-gate SiC MOSFET with an embedded MOS-channel diode for enhanced third-quadrant and switching performances is proposed and studied using TCAD simulations in this paper. During the freewheeling period, the MOS-channel diode with a low potential barrier constrains the reverse current flow through it. Therefore, the suggested device not only has a low diode cut-in voltage but also entirely suppresses the intrinsic body diode, which will cause bipolar deterioration. In order to clarify the barrier-lowering effect of the MOS-channel diode, an analytical model is proposed. The calibrated simulation results demonstrate that the diode cut-in voltage of the proposed device is decreased from the conventional voltage of 2.7 V to 1.2 V. In addition, due to the split-gate structure, the gate-to-drain charge () of the proposed device is 20 nC/cm, and the reverse-transfer capacitance () is 14 pF/cm, which are lower than the of 230 nC/cm and the of 105 pF/cm for the conventional one. Therefore, a better high-frequency figure-of-merit and lower switching loss are obtained.
本文提出了一种新型的具有嵌入式MOS沟道二极管的分裂栅碳化硅金属氧化物半导体场效应晶体管(SiC MOSFET),用于增强第三象限和开关性能,并使用TCAD模拟进行了研究。在续流期间,具有低势垒的MOS沟道二极管会限制反向电流通过。因此,所建议的器件不仅具有低二极管导通电压,而且完全抑制了会导致双极恶化的本征体二极管。为了阐明MOS沟道二极管的势垒降低效应,提出了一种解析模型。校准后的模拟结果表明,所建议器件的二极管导通电压从传统的2.7 V降至1.2 V。此外,由于分裂栅结构,所建议器件的栅极至漏极电荷()为20 nC/cm,反向传输电容()为14 pF/cm,低于传统器件的230 nC/cm和105 pF/cm。因此,获得了更好的高频品质因数和更低的开关损耗。