Ou Yangjie, Lan Zhong, Hu Xiarong, Liu Dong
School of Electrical Engineering, Southwest Jiaotong University, Chengdu 611756, China.
School of Science, Xihua University, Chengdu 610039, China.
Micromachines (Basel). 2024 Feb 8;15(2):254. doi: 10.3390/mi15020254.
A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop () at = 100 A/cm, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (). Additionally, the gate-drain capacitance () and gate-drain charge () of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.
提出了一种在栅极沟槽中嵌入低势垒二极管和L形栅源结构的碳化硅双沟槽金属氧化物半导体场效应晶体管(SiC double - trench MOSFET),并通过二维模拟对其进行了研究。该晶体管表现出改善的反向传导和开关性能。与双沟槽MOSFET(DT - MOS)和带有沟道MOS二极管的DT - MOS(DTC - MOS)相比,所提出的MOS在100 A/cm²时具有更低的电压降(),这可以在相同的阻断电压(BV)下防止双极退化,并降低最大氧化层电场()。此外,由于源极延伸到栅极底部,所提出的MOSFET的栅漏电容()和栅漏电荷()显著降低,并且栅电极和漏电极之间的重叠减少。尽管所提出的MOS比DT - MOS和DTC - MOS具有更大的,但它具有更低的开关损耗,在高频应用中具有更大优势。