Oh Jong Hyeok, Yu Yun Seop
ICT & Robotics Engineering, Semiconductor Convergence Engineering, AISPC Laboratory and IITC, Hankyong National University, 327 Jungang-ro, Anseong-si 17579, Gyenggi-do, Republic of Korea.
Micromachines (Basel). 2023 Sep 23;14(10):1822. doi: 10.3390/mi14101822.
In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide-nitride-oxide layer and a metal-oxide-semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and -18 V for 1 μs, respectively. The memory window of the M3D-NVM-FBFET was 1.98 V. As the retention simulation was conducted for 10 years, the memory window decreased from 1.98 to 0.83 V. For the M3D-NVM-FBFET, the electrical coupling that occurs through an electrical signal in the bottom-tier transistor was investigated. As the thickness of the interlayer dielectric () decreases from 100 to 10 nm, the change in the increases from 0.16 to 0.87 V and from 0.15 to 0.84 V after the programming and erasing operations, respectively. M3D-NVM-FBFET circuits with a thin of 50 nm or less need to be designed considering electrical coupling.
在本研究中，使用技术计算机辅助设计研究了由反馈场效应晶体管构成的单片三维非易失性存储器（M3D-NVM-FBFET）的电学特性和电耦合效应。M3D-NVM-FBFET由一个带有氮氧化物层的N型FBFET和分别位于顶层和底层的一个金属氧化物半导体场效应晶体管（MOSFET）组成。对于存储器模拟，编程电压和擦除电压分别在18 V和 -18 V下施加1 μs。M3D-NVM-FBFET的存储窗口为1.98 V。在进行10年的保持模拟时，存储窗口从1.98 V降至0.83 V。对于M3D-NVM-FBFET，研究了底层晶体管中通过电信号发生的电耦合。当层间电介质（）的厚度从100 nm减小到10 nm时，编程和擦除操作后，存储窗口的变化分别从0.16 V增加到0.87 V和从0.15 V增加到0.84 V。需要考虑电耦合来设计层间电介质厚度为50 nm或更小的M3D-NVM-FBFET电路。
