Zhang Penghao, Yao Chenguo, Yu Liang, He Yingjiang, Dong Shoulong
State Key Laboratory of Power Transmission Equipment Technology, School of Electrical Engineering, Chongqing University, Chongqing 400030, China.
ACS Appl Mater Interfaces. 2023 Nov 15;15(45):53031-53042. doi: 10.1021/acsami.3c14057. Epub 2023 Nov 3.
Insufficient surface insulation margin is the primary challenge for a 10 kV plus high-voltage semiconductor module. Surface charge accumulation and electric field distortion are the leading causes of surface insulation failure. Power modules restrict leakage loss, so only insulation dielectrics with low surface conductivity can be used. However, low conductivity, accumulated charge dissipation, and distorted electric field optimization have always been contradictory. A potential barrier increase and electron affinity decrease are both less coupled approaches with conductivity, which may have the potential for reducing surface charge accumulation. Here, surface charge accumulation inhibition and local electric field optimization were synchronously realized by tailored coating deposition with colliding plasma jets. This novelty approach leads to a finer interfacial modification of the triple junction and its nearby interfaces. The high-barrier and low-affinity coatings deposited by colliding plasma jets suppress charge injection (electrode-polymer interface) and promote charge dissipation (gas-polymer interface), respectively. At the same time, the small-area semiconductor deposited at the triple junction relieves the distortion of the electric field. In the end, while maintaining a low leakage current, the surface flashover voltages of polytetrafluoroethylene, polyimide, and epoxy packaging polymers are significantly increased by 69.7, 43.2, and 39.6%, respectively. Notably, the normalized leakage loss is less than 3/10,000 of the commercially available SiC module, which vastly differs from the surface insulation improvement strategy that blindly increases surface conductivity. This tailored coating modification strategy provides a new idea for dielectric research. It has reasonable practicability due to fast, cheap, and environmentally friendly colliding plasma jets.
对于10 kV及以上的高压半导体模块而言，表面绝缘裕度不足是主要挑战。表面电荷积累和电场畸变是表面绝缘失效的主要原因。功率模块限制泄漏损耗，因此只能使用表面电导率低的绝缘电介质。然而，低电导率、积累电荷耗散和畸变电场优化一直相互矛盾。势垒增加和电子亲和力降低与电导率的耦合程度都较低，这可能具有减少表面电荷积累的潜力。在此，通过采用碰撞等离子体射流进行定制涂层沉积，同步实现了表面电荷积累抑制和局部电场优化。这种新颖的方法导致三结及其附近界面的界面改性更精细。通过碰撞等离子体射流沉积的高势垒和低亲和力涂层分别抑制电荷注入（电极 - 聚合物界面）和促进电荷耗散（气体 - 聚合物界面）。同时，沉积在三结处的小面积半导体缓解了电场畸变。最终，在保持低泄漏电流的同时，聚四氟乙烯、聚酰亚胺和环氧封装聚合物的表面闪络电压分别显著提高了69.7%、43.2%和39.6%。值得注意的是，归一化泄漏损耗小于市售碳化硅模块的万分之三，这与盲目提高表面电导率的表面绝缘改进策略有很大不同。这种定制涂层改性策略为电介质研究提供了新思路。由于碰撞等离子体射流快速、廉价且环保，具有合理的实用性。
