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用于MOS器件的具有SiO中间层的高κ氧化物XO/金刚石(X = Hf和Zr)界面处能带对准的理论洞察。

Theoretical Insight into the Band Alignment at High-κ Oxide XO/Diamond (X = Hf and Zr) Interfaces with a SiO Interlayer for MOS Devices.

作者信息

Cheng Chunmin, Sun Xiang, Gui Qingzhong, Wu Gai, Shen Wei, Dong Fang, Liu Yonghui, Robertson John, Zhang Zhaofu, Guo Yuzheng, Liu Sheng

机构信息

The Institute of Technological Sciences, Wuhan University, Wuhan 430072, China.

School of Power and Mechanical Engineering, Wuhan University, Wuhan 430072, China.

出版信息

ACS Appl Mater Interfaces. 2024 May 15;16(19):25581-25588. doi: 10.1021/acsami.4c03261. Epub 2024 May 6.

Abstract

Diamond has become a promising candidate for high-power devices based on its ultrawide bandgap and excellent thermoelectric properties, where an appropriate gate dielectric has been a bottleneck hindering the development of diamond devices. Herein, we have systematically investigated the structural arrangement and electronic properties of diamond/high-κ oxide (HfO, ZrO) heterojunctions by first-principles calculations with a SiO interlayer. Charge analysis reveals that the C-Si bonding interface attracts a large amount of charge concentrated at the diamond interface, indicating the potential for the formation of a 2D hole gas (2DHG). The diamond/HfO and diamond/ZrO heterostructures exhibit similar "Type II" band alignments with VBOs of 2.47 and 2.21 eV, respectively, which is consistent with experimental predictions. The introduction of a SiO dielectric layer into the diamond/SiO/high-κ stacks exhibits the typical "Type I″ straddling band offsets (BOs). In addition, the wide bandgap SiO interlayer keeps the valence band maximum (VBM) and conduction band minimum (CBM) in the stacks away from those of diamond, effectively confining the electrons and holes in MOS devices. This work exhibits the potential of SiO/high-κ oxide gate dielectrics for diamond devices and provides theoretical insights into the rational design of high-quality gate dielectrics for diamond-based MOS device applications.

摘要

基于其超宽带隙和优异的热电性能,金刚石已成为高功率器件的一个有前景的候选材料,然而,合适的栅极电介质一直是阻碍金刚石器件发展的瓶颈。在此,我们通过含SiO中间层的第一性原理计算,系统地研究了金刚石/高κ氧化物(HfO、ZrO)异质结的结构排列和电子性质。电荷分析表明,C-Si键合界面吸引了大量集中在金刚石界面的电荷,这表明形成二维空穴气(2DHG)的潜力。金刚石/HfO和金刚石/ZrO异质结构表现出类似的“II型”能带排列,其价带偏移(VBO)分别为2.47和2.21 eV,这与实验预测一致。在金刚石/SiO/高κ堆叠结构中引入SiO介电层表现出典型的“I型”跨带偏移(BO)。此外,宽带隙SiO中间层使堆叠结构中的价带最大值(VBM)和导带最小值(CBM)与金刚石的不同,有效地限制了MOS器件中的电子和空穴。这项工作展示了SiO/高κ氧化物栅极电介质在金刚石器件中的潜力,并为基于金刚石的MOS器件应用中高质量栅极电介质的合理设计提供了理论见解。

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