González César, Ruiz Mariano, Carpeño Antonio, Piñas Alejandro, Cano-Ott Daniel, Plaza Julio, Martinez Trino, Villamarin David
Instrumentation and Applied Acoustic Research Group, Universidad Politécnica de Madrid, 28031 Madrid, Spain.
Centro de Investigaciones Energéticas, Medioambientales y Tecnológicas (CIEMAT), 28040 Madrid, Spain.
Sensors (Basel). 2024 Apr 25;24(9):2724. doi: 10.3390/s24092724.
The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extracts the physically relevant parameters from the detected BC501A signals. The hardware solution is implemented in a MicroTCA system that provides the physical, mechanical, electrical, and cooling support for an AMC board (NAMC-ZYNQ-FMC) with a Xilinx ZYNQ Ultrascale-MP SoC. The Xilinx FPGA programmable logic implements a JESD204B interface to high-speed ADCs. The physical and datalink JESD204B layers are implemented using hardware description language (HDL), while the Xilinx high-level synthesis language (HLS) is used for the transport and application layers. The DPSA algorithm is a JESD204B application layer that includes a FIR filter and a constant fraction discriminator (CFD) function, a baseline calculation function, a peak detection function, and an energy calculation function. This architecture achieves an analysis mean time of less than 100 µs per signal with an FPGA resource utilization of about 50% of its most used resources. This paper presents a high-performance DPSA embedded system that interfaces with a 1 GS/s ADC and performs accurate calculations with relatively low latency.
BC501A传感器是一种常用于核物理中检测快中子的液体闪烁体。本文描述了一种用于实时分析的数字脉冲形状分析（DPSA）的硬件实现。DPSA是一种从检测到的BC501A信号中提取物理相关参数的算法。硬件解决方案在一个MicroTCA系统中实现，该系统为带有赛灵思ZYNQ Ultrascale-MP SoC的AMC板（NAMC-ZYNQ-FMC）提供物理、机械、电气和冷却支持。赛灵思FPGA可编程逻辑实现了与高速ADC的JESD204B接口。物理层和数据链路层的JESD204B使用硬件描述语言（HDL）实现，而赛灵思高级合成语言（HLS）用于传输层和应用层。DPSA算法是一个JESD204B应用层，包括一个FIR滤波器和一个恒比鉴别器（CFD）函数、一个基线计算函数、一个峰值检测函数和一个能量计算函数。该架构实现了每个信号的分析平均时间小于100微秒，FPGA资源利用率约为其最常用资源的50%。本文提出了一种高性能的DPSA嵌入式系统，该系统与1 GS/s ADC接口，并以相对较低的延迟进行精确计算。
