Kim Nam-Seog
Department of Information and Communication Engineering, School of Electrical and Computer Engineering, Chungbuk National University, Cheongju-si 28644, Republic of Korea.
Sensors (Basel). 2024 Aug 14;24(16):5255. doi: 10.3390/s24165255.
To establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully integrated all-digital phase-locked loop (ADPLL)-based Gaussian frequency shift keying (GFSK) modulator incorporating two-point modulation (TPM). The modulator aims to enhance the efficiency of BLE communication in these networks. The design includes a time-to-digital converter (TDC) with the following three key features to improve linearity and time resolution: fast settling time, low dropout regulators (LDOs) that adapt to process, voltage, and temperature (PVT) variations, and interpolation assisted by an analog-to-digital converter (ADC). It features a digital controlled oscillator (DCO) with two key enhancements as follows: ΔΣ modulator dithering and hierarchical capacitive banks, which expand the frequency tuning range and improve linearity, and an integrated, fast-converging least-mean-square (LMS) algorithm for DCO gain calibration, which ensures compliance with BLE 5.0 stable modulation index (SMI) requirements. Implemented in a 28 nm CMOS process, occupying an active area of 0.33 mm, the modulator demonstrates a wide frequency tuning range of from 2.21 to 2.58 GHz, in-band phase noise of -102.1 dBc/Hz, and FSK error of 1.42% while consuming 1.6 mW.
为了建立无处不在且节能的无线传感器网络（WSN），短距离物联网（IoT）设备需要工作在2.4 GHz的蓝牙低功耗（BLE）技术。本研究提出了一种新颖的方法：一种基于全集成全数字锁相环（ADPLL）的高斯频移键控（GFSK）调制器，采用两点调制（TPM）。该调制器旨在提高这些网络中BLE通信的效率。该设计包括一个具有以下三个关键特性的时间数字转换器（TDC），以提高线性度和时间分辨率：快速建立时间、适应工艺、电压和温度（PVT）变化的低压差稳压器（LDO）以及由模数转换器（ADC）辅助的插值。它具有一个数字控制振荡器（DCO），有以下两个关键改进：ΔΣ调制器抖动和分层电容组，可扩展频率调谐范围并提高线性度，以及用于DCO增益校准的集成快速收敛最小均方（LMS）算法，可确保符合BLE 5.0稳定调制指数（SMI）要求。该调制器采用28 nm CMOS工艺实现，占用有源面积0.33 mm²，具有2.21至2.58 GHz的宽频率调谐范围、-102.1 dBc/Hz的带内相位噪声以及1.42%的FSK误差，同时功耗为1.6 mW。
