Extremely Low Thermal Resistance of β-GaO MOSFETs by Co-integrated Design of Substrate Engineering and Device Packaging.

Gallium oxide (GaO) emerges as a promising ultrawide bandgap semiconductor, which is expected to surpass the performance of current wide bandgap materials, like GaN and SiC, in electronic devices. However, widespread application of GaO is hindered by its extremely low thermal conductivity and lack of effective device-level thermal management strategies. In this work, GaO metal-oxide-semiconductor field-effect transistors (MOSFETs) are fabricated by conducting co-integrated design of substrate engineering with layer transferring and device packaging. 3D Raman thermography is introduced as a novel method to analyze the temperature distribution within the device, which provides valuable insights into their thermal performances. A high-quality GaO-SiC heterogeneous integrated material is successfully fabricated with an extremely low interface thermal resistance of 6.67 ± 2 m·K/GW. Compared to the homoepitaxial GaO MOSFETs, the degradation of / in GaO-SiC MOSFETs is decreased by 1.5 orders of magnitude, and that of is decreased by 31%, showing the great thermal stability of GaO-SiC MOSFETs. With the additional device packaging, a significant one order-of-magnitude reduction in the thermal resistance of the GaO-SiC MOSFET is achieved, reaching a record-low value of 4.45 K·mm/W in the reported GaO MOSFETs. This work demonstrates an efficient strategy for device-level thermal management in next-generation GaO power and RF applications.