Pratapsi Sagar Silva, Cruz Diogo, André Paulo
Instituto Superior Técnico, Universidade de Lisboa, Lisbon, Portugal.
Instituto de Telecomunicações, Lisbon, Portugal.
Sci Rep. 2024 Oct 29;14(1):26042. doi: 10.1038/s41598-024-76396-9.
Quantum computation holds the promise of solving computational problems which are believed to be classically intractable. However, in practice, quantum devices are still limited by their relatively short coherence times and imperfect circuit-hardware mapping. In this work, we present the parallelization of pre-calibrated pulses at the hardware level as an easy-to-implement strategy to optimize quantum gates. Focusing on gates, we demonstrate that such parallelization leads to improved fidelity and gate time reduction, when compared to serial concatenation. As measured by Cycle Benchmarking and Process Tomography, we reduce gate errors by half. We show that this strategy can be applied to other gates like the CNOT and CZ, and it may benefit tasks such as Hamiltonian simulation problems, amplitude amplification, and error-correction codes.
量子计算有望解决被认为传统上难以处理的计算问题。然而，在实践中，量子设备仍然受到其相对较短的相干时间和不完善的电路-硬件映射的限制。在这项工作中，我们提出在硬件层面并行化预校准脉冲，作为一种易于实现的优化量子门的策略。聚焦于特定门，我们证明与串行级联相比，这种并行化可提高保真度并减少门时间。通过循环基准测试和过程层析成像测量，我们将门错误减少了一半。我们表明这种策略可应用于其他门，如CNOT门和CZ门，并且它可能有益于诸如哈密顿量模拟问题、振幅放大和纠错码等任务。
