Grace Carl, Garcia-Sciveres Maurice, Heim Timon, Krieger Amanda
Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA.
Sensors (Basel). 2025 Apr 3;25(7):2284. doi: 10.3390/s25072284.
Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm.
精确计时是新兴的4D粒子跟踪、正电子发射断层扫描（PET）、束流和聚变等离子体诊断以及其他系统的关键要求。时间数字转换器（TDC）通常用于提供事件之间相对计时的数字估计，但TDC的抖动性能不会优于采集脉冲并将其传输到TDC的电路的性能。对几种时钟接收器和分配电路进行了评估，并制造了一种带有电阻负载的差分放大器，该放大器驱动一个伪差分时钟分配网络，该网络是根据抗辐射和低温兼容性的设计准则开发的，作为三个原型的一部分：一个用于高精度计时像素读出的模拟前端测试平台芯片、一个专用TDC评估芯片和一个低增益雪崩探测器（LGAD）读出电路。基于对原型的TDC测量，我们推断时钟接收器和分配电路增加的抖动小于2.25 ps-rms。这一性能满足了许多未来精确计时系统的要求。时钟接收器和片上伪差分驱动器采用商用28纳米CMOS技术制造，占用面积为2288平方微米。
