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一种使铁电印记效应最小化的电极设计策略。

An Electrode Design Strategy to Minimize Ferroelectric Imprint Effect.

作者信息

Chen Yu-Wei, Yu Tung-Yuan, Huang Chun-Wei, Yu Tzu-Hsuan, Su Yung-Chi, Chen Chao-Rung, Hung Wei-Chen, Chang Pei-Yin, Prasad Bhagwati, Lin Yu-Chuan, Ramesh Ramamoorthy, Huang Yen-Lin

机构信息

Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu, 300093, Taiwan.

Taiwan Semiconductor Research Institute, Hsinchu, 300091, Taiwan.

出版信息

Adv Sci (Weinh). 2025 Aug;12(29):e70011. doi: 10.1002/advs.70011. Epub 2025 May 22.

DOI:10.1002/advs.70011
PMID:40402000
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC12362776/
Abstract

The phenomenon of ferroelectric imprint, characterized by an asymmetric polarization switching behavior, poses significant challenges in the reliability and performance of ultra-low-voltage ferroelectric devices, including MagnetoElectric Spin-Orbit devices, Ferroelectric Random-Access Memory, Ferroelectric Field-Effect Transistors, and Ferroelectric Tunnel Junctions. In this study, the influence of electrode configuration in different device architectures are systematically investigated on their imprint effect. By tuning the work function of LaSrMnO (LSMO) electrodes through oxygen pressure during deposition, precise control over the built-in voltage offset (V) in ferroelectric capacitors are demonstrated. This results reveal that higher oxygen pressures increase the work function of LSMO, effectively compensating for V and enhancing device stability. Finally, a ferroelectric device with a hybrid bottom electrode of LSMO and SrRuO is optimized to mitigate the imprint effect. The optimal device showcases small coercive voltage of 0.3 V, a minimal V of 0.06 V, excellent endurance (electrical cycle up to 10), and robust zero bias applied polarization retention. These findings provide a practical guideline for electrode design in ferroelectric devices, addressing the imprint effect and improving operational reliability. This approach, combining material tuning and in situ diagnostics, offers a pathway to optimize ferroelectric device performance, with implications for advancing ultra-low-power electronics.

摘要

铁电印记现象表现为不对称的极化切换行为,这给包括磁电自旋轨道器件、铁电随机存取存储器、铁电场效应晶体管和铁电隧道结在内的超低电压铁电器件的可靠性和性能带来了重大挑战。在本研究中,系统地研究了不同器件架构中电极配置对其印记效应的影响。通过在沉积过程中通过氧压调节LaSrMnO(LSMO)电极的功函数,展示了对铁电电容器中内置电压偏移(V)的精确控制。这些结果表明,较高的氧压会增加LSMO的功函数,有效补偿V并提高器件稳定性。最后,对具有LSMO和SrRuO混合底部电极的铁电器件进行了优化,以减轻印记效应。优化后的器件具有0.3 V的小矫顽电压、0.06 V的最小V、出色的耐久性(高达10次电循环)和强大的零偏置施加极化保持能力。这些发现为铁电器件的电极设计提供了实用指南,解决了印记效应并提高了操作可靠性。这种结合材料调节和原位诊断的方法为优化铁电器件性能提供了一条途径,对推动超低功耗电子学具有重要意义。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/eb5b/12362776/dbad248c0d89/ADVS-12-e70011-g001.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/eb5b/12362776/4cf0388b4179/ADVS-12-e70011-g002.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/eb5b/12362776/d754f4d8329d/ADVS-12-e70011-g005.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/eb5b/12362776/179b7e43ecff/ADVS-12-e70011-g004.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/eb5b/12362776/dbad248c0d89/ADVS-12-e70011-g001.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/eb5b/12362776/4cf0388b4179/ADVS-12-e70011-g002.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/eb5b/12362776/d754f4d8329d/ADVS-12-e70011-g005.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/eb5b/12362776/179b7e43ecff/ADVS-12-e70011-g004.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/eb5b/12362776/dbad248c0d89/ADVS-12-e70011-g001.jpg

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